数字钟vhdl程序代码源
作者&投稿：绽威 （若有异议请与网页底部的电邮联系）
课程设计任务书 课程设计名称 EDA课程设计 学生姓名 专业班级 设计题目 多功能数字钟设计 一、课程设计目的 1、综合运用EDA技术，独立完成一个课题的设计，考察运用所学知识，解决实际问题的能力； 2、结合理论知识，考察阅读参考资料、文献、手VHDL数字时钟完整程序代码（要求要有元件例化，并
程序启动，校时，校分使能输入
校对用的加减输入
时分秒显示输出
根据CLK进行“秒”的累加，逐次进行进位判断。“时”就根据“分”的进位判断。这是数字电路连线的思路啦。呵呵
http://zhidao.baidu.com/question/76922909.html
还可以参考一下这个，要方便的多
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity clock_shu is
port(
clk : in std_logic;
reset : in std_logic;
duan : out std_logic_vector(5 downto 0);
data_o : out std_logic_vector(7 downto 0)
);
end;
architecture a of clock_shu is
component count60
port(
carry : std_logic;
rst : std_logic;
times : out integer range 0 to 59;
full : out std_logic
);
end component;
component count24
port(
carry : in std_logic;
rst : in std_logic;
times : out integer range 0 to 23
--full : out std_logic
);
end component;
component i60bcd
port(
interg : in integer range 0 to 59;
ten : out std_logic_vector(7 downto 0);
one : out std_logic_vector(7 downto 0)
);
end component;
component i24bcd
port(
interg : in integer range 0 to 23;
ten : out std_logic_vector(7 downto 0);
one : out std_logic_vector(7 downto 0)
);
end component;
signal carry1,carry2 : std_logic;
signal abin1,abin2 : integer range 0 to 59;
signal abin3 : integer range 0 to 23;
signal clk_1h : std_logic;
signal sh,sl,mh,ml,hh,hl : std_logic_vector(7 downto 0);
signal cnt : integer range 0 to 5 :=0;
begin
process(clk)--分频为1hz
constant counter_len:integer:=19999999;
variable cnt:integer range 0 to counter_len;
begin
if clk'event and clk='1' then
if cnt=counter_len then
cnt:=0;
else
cnt:=cnt+1;
end if;
case cnt is
when 0 to counter_len/2=>clk_1h<='0';
when others =>clk_1h<='1';
end case;
end if;
end process;
process(clk)
variable cnt1 : integer range 0 to 200;
variable cnt2 : integer range 0 to 10;
begin
if clk'event and clk='1' then
if cnt1=200 then
cnt1:=0;
if cnt2=10 then
cnt2:=0;
if(cnt=5)then
cnt<=0;
else
cnt<=cnt+1;
end if;
else
cnt2:=cnt2+1;
end if;
else
cnt1:=cnt1+1;
end if;
end if;
end process;
process(clk)
begin
if clk='1' then
case cnt is
when 0 => duan<="000001";data_o<=sl;
when 1 => duan<="000010";data_o<=sh;
when 2 => duan<="000100";data_o<=ml;
when 3 => duan<="001000";data_o<=mh;
when 4 => duan<="010000";data_o<=hl;
when 5 => duan<="100000";data_o<=hh;
when others=>duan<="000000";
end case;
end if;
end process;
u1 : count60 port map(carry=>clk_1h,rst=>reset,times=>abin1,full=>carry1);
u2 : count60 port map(carry=>carry1,rst=>reset,times=>abin2,full=>carry2);
u3 : count24 port map(carry=>carry2,rst=>reset,times=>abin3);
u4 : i60bcd port map(interg=>abin1,ten=>sh,one=>sl);
u5 : i60bcd port map(interg=>abin2,ten=>mh,one=>ml);
u6 : i24bcd port map(interg=>abin3,ten=>hh,one=>hl);
end;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count60 is--分，秒计数器
port(
carry : std_logic;
rst : std_logic;
times : out integer range 0 to 59;
full : out std_logic
);
end;
architecture a of count60 is
signal time_s : integer range 0 to 59;
begin
process(rst,carry)
begin
if rst='1' then
time_s<=0;
full<='0';
elsif rising_edge(carry) then
if time_s=59 then
time_s<=0;
full<='1';
else
time_s<=time_s+1;
full<='0';
end if;
end if;
end process;
times<=time_s;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count24 is--时计数器
port(
carry : in std_logic;
rst : in std_logic;
times : out integer range 0 to 23
--full : out std_logic
);
end;
architecture a of count24 is
signal time_s : integer range 0 to 23;
begin
process(rst,carry)
begin
if rst='1' then
time_s<=0;
--full<='0';
elsif rising_edge(carry) then
if time_s=23 then
time_s<=0;
--full<='1';
else
time_s<=time_s+1;
--full<='1';
end if;
end if;
end process;
times<=time_s;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity i60bcd is--分，秒显示
port(
interg : in integer range 0 to 59;
ten : out std_logic_vector(7 downto 0);
one : out std_logic_vector(7 downto 0)
);
end;
architecture a of i60bcd is
begin
process(interg)
begin
case interg is
when 0|10|20|30|40|50 => one<="11000000";
when 1|11|21|31|41|51 => one<="11111001";
when 2|12|22|32|42|52 => one<="10100100";
when 3|13|23|33|43|53 => one<="10110000";
when 4|14|24|34|44|54 => one<="10011001";
when 5|15|25|35|45|55 => one<="10010010";
when 6|16|26|36|46|56 => one<="10000011";
when 7|17|27|37|47|57 => one<="11111000";
when 8|18|28|38|48|58 => one<="10000000";
when 9|19|29|39|49|59 => one<="10011000";
when others => one<=null;
end case;
case interg is
when 0|1|2|3|4|5|6|7|8|9 => ten<="11000000";
when 10|11|12|13|14|15|16|17|18|19 => ten<="11111001";
when 20|21|22|23|24|25|26|27|28|29 => ten<="10100100";
when 30|31|32|33|34|35|36|37|38|39 => ten<="10110000";
when 40|41|42|43|44|45|46|47|48|49 => ten<="10011001";
when 50|51|52|53|54|55|56|57|58|59 => ten<="10010010";
when others => ten<=null;
end case;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity i24bcd is--时显示
port(
interg : in integer range 0 to 23;
ten : out std_logic_vector(7 downto 0);
one : out std_logic_vector(7 downto 0)
);
end;
architecture a of i24bcd is
begin
process(interg)
begin
case interg is
when 0|10|20 => one<="11000000";
when 1|11|21 => one<="11111001";
when 2|12|22 => one<="10100100";
when 3|13|23 => one<="10110000";
when 4|14 => one<="10011001";
when 5|15 => one<="10010010";
when 6|16 => one<="10000011";
when 7|17 => one<="11111000";
when 8|18 => one<="10000000";
when 9|19 => one<="10011000";
when others => one<=null;
end case;
case interg is
when 0|1|2|3|4|5|6|7|8|9 => ten<="11000000";
when 10|11|12|13|14|15|16|17|18|19 => ten<="11111001";
when 20|21|22|23 => ten<="10100100";
when others => ten<=null;
end case;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MINSECONDb is
port(clk,clrm,stop:in std_logic;----时钟/清零信号
secm1,secm0:out std_logic_vector(3 downto 0);----秒高位/低位
co:out std_logic);-------输出/进位信号
end MINSECONDb;
architecture SEC of MINSECONDb is
signal clk1,DOUT2:std_logic;
begin
process(clk,clrm)
variable cnt1,cnt0:std_logic_vector(3 downto 0);---计数
VARIABLE COUNT2 :INTEGER RANGE 0 TO 10 ;
begin
IF CLK'EVENT AND CLK='1'THEN
IF COUNT2>=0 AND COUNT2<10 THEN
COUNT2:=COUNT2+1;
ELSE COUNT2:=0;
DOUT2<= NOT DOUT2;
END IF;
END IF;
if clrm='1' then----当clr为1时，高低位均为0
cnt1:="0000";
cnt0:="0000";
elsif clk'event and clk='1' then
if stop='1' then
cnt0:=cnt0;
cnt1:=cnt1;
end if;
if cnt1="1001" and cnt0="1000" then----当记数为98（实际是经过59个记时脉冲）
co<='1';----进位
cnt0:="1001";----低位为9
elsif cnt0<"1001" then----小于9时
cnt0:=cnt0+1;----计数
--elsif cnt0="1001" then
--clk1<=not clk1;
else
cnt0:="0000";
if cnt1<"1001" then----高位小于9时
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
secm1<=cnt1;
secm0<=cnt0;
end process;
end SEC;
秒模块程序清单
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SECOND is
port(clk,clr:in std_logic;----时钟/清零信号
sec1,sec0:out std_logic_vector(3 downto 0);----秒高位/低位
co:out std_logic);-------输出/进位信号
end SECOND;
architecture SEC of SECOND is
begin
process(clk,clr)
variable cnt1,cnt0:std_logic_vector(3 downto 0);---计数
begin
if clr='1' then----当ckr为1时，高低位均为0
cnt1:="0000";
cnt0:="0000";
elsif clk'event and clk='1' then
if cnt1="0101" and cnt0="1000" then----当记数为58（实际是经过59个记时脉冲）
co<='1';----进位
cnt0:="1001";----低位为9
elsif cnt0<"1001" then----小于9时
cnt0:=cnt0+1;----计数
else
cnt0:="0000";
if cnt1<"0101" then----高位小于5时
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
sec1<=cnt1;
sec0<=cnt0;
end process;
end SEC;
分模块程序清单
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MINUTE is
port(clk,en:in std_logic;
min1,min0:out std_logic_vector(3 downto 0);
co:out std_logic);
end MINUTE;
architecture MIN of MINUTE is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clk'event and clk='1' then
if en='1' then
if cnt1="0101" and cnt0="1000" then
co<='1';
cnt0:="1001";
elsif cnt0<"1001" then
cnt0:=cnt0+1;
else
cnt0:="0000";
if cnt1<"0101" then
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
end if;
min1<=cnt1;
min0<=cnt0;
end process;
end MIN;
时模块程序清单
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity HOUR is
port(clk,en:in std_logic;----输入时钟/高电平有效的使能信号
h1,h0:out std_logic_vector(3 downto 0));----时高位/低位
end HOUR;
architecture hour_arc of HOUR is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);----记数
begin
if clk'event and clk='1' then---上升沿触发
if en='1' then---同时“使能”为1
if cnt1="0010" and cnt0="0011" then
cnt1:="0000";----高位/低位同时为0时
cnt0:="0000";
elsif cnt0<"1001" then----低位小于9时，低位记数累加
cnt0:=cnt0+1;
else
cnt0:="0000";
cnt1:=cnt1+1;-----高位记数累加
end if;
end if;
end if;
h1<=cnt1;
h0<=cnt0;
end process;
end hour_arc;
动态扫描模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity SELTIME is
port(
clk:in std_logic;------扫描时钟
secm1,secm0,sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0);-----分别为秒个位/时位；分个位/
daout:out std_logic_vector(3 downto 0);----------------输出
sel:out std_logic_vector(2 downto 0));-----位选信号
end SELTIME;
architecture fun of SELTIME is
signal count:std_logic_vector(2 downto 0);----计数信号
begin
sel<=count;
process(clk)
begin
if(clk'event and clk='1') then
if(count>="111") then
count<="000";
else
count<=count+1;
end if;
end if;
case count is
when"111"=>daout<= secm0;----秒个位
when"110"=>daout<= secm1;----秒十位
when"101"=>daout<= sec0;----分个位
when"100"=>daout<= sec1;----分十位
when"011"=>daout<=min0; ----时个位
when"010"=>daout<=min1;----时十位
when"001"=>daout<=h0;
when others =>daout<=h1;
end case;
end process;
end fun;
报时模块
library ieee;
use ieee.std_logic_1164.all;
entity ALERT is
port(m1,m0,s1,s0:in std_logic_vector(3 downto 0);------输入秒、分高/低位信号
clk:in std_logic;------高频声控制
q500,qlk:out std_logic);----低频声控制
end ALERT;
architecture sss_arc of ALERT is
begin
process(clk)
begin
if clk'event and clk='1' then
if m1="0101" and m0="1001" and s1="0101" then----当秒高位为5，低位为9时且分高位为5
if s0="0001" or s0="0011" or s0="0101" or s0="0111" then---当分的低位为1或3或5或7时
q500<='1';----低频输出为1
else
q500<='0';----否则输出为0
end if;
end if;
if m1="0101" and m0="1001" and s1="0101" and s0="1001" then---当秒高位为5，低位为9时且分高位为5，----分低位为9时，也就是“59分59秒”的时候“报时”
qlk<='1';-----高频输出为1
else
qlk<='0';
end if;
end if;
end process;
end sss_arc;
显示模块
library ieee;
use ieee.std_logic_1164.all;
entity DISPLAY is
port(d:in std_logic_vector(3 downto 0);----连接seltime扫描部分d信号
q:out std_logic_vector(6 downto 0));----输出段选信号（电平）
end DISPLAY;
architecture disp_are of DISPLAY is
begin
process(d)
begin
case d is
when"0000" =>q<="0111111";--显示0
when"0001" =>q<="0000110";--显示1
when"0010" =>q<="1011011";--显示2
when"0011" =>q<="1001111";--显示3
when"0100" =>q<="1100110";--显示4
when"0101" =>q<="1101101";--显示5
when"0110" =>q<="1111101";--显示6
when"0111" =>q<="0100111";--显示7
when"1000" =>q<="1111111";--显示8
when others =>q<="1101111";--显示9
end case;
end process;
end disp_are;
顶层文件（原理图输入）
********************************************************************
数字钟设计模块与程序（不含秒表）
*********************************************************************
1.分频模块（原理图输入）
2. 秒模块程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SECOND is
port(clk,clr:in std_logic;
sec1,sec0:out std_logic_vector(3 downto 0);
co:out std_logic);
end SECOND;
architecture SEC of SECOND is
begin
process(clk,clr)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clr='1' then
cnt1:="0000";
cnt0:="0000";
elsif clk'event and clk='1' then
if cnt1="0101" and cnt0="1000" then
co<='1';
cnt0:="1001";
elsif cnt0<"1001" then
cnt0:=cnt0+1;
else
cnt0:="0000";
if cnt1<"0101" then
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
sec1<=cnt1;
sec0<=cnt0;
end process;
end SEC;
3.分模块程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MINUTE is
port(clk,en:in std_logic;
min1,min0:out std_logic_vector(3 downto 0);
co:out std_logic);
end MINUTE;
architecture MIN of MINUTE is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clk'event and clk='1' then
if en='1' then
if cnt1="0101" and cnt0="1000" then
co<='1';
cnt0:="1001";
elsif cnt0<"1001" then
cnt0:=cnt0+1;
else
cnt0:="0000";
if cnt1<"0101" then
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
end if;
min1<=cnt1;
min0<=cnt0;
end process;
end MIN;
4.时模块程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity HOUR is
port(clk,en:in std_logic;
h1,h0:out std_logic_vector(3 downto 0));
end HOUR;
architecture hour_arc of HOUR is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clk'event and clk='1' then
if en='1' then
if cnt1="0010" and cnt0="0011" then
cnt1:="0000";
cnt0:="0000";
elsif cnt0<"1001" then
cnt0:=cnt0+1;
end if;
end if;
end if;
h1<=cnt1;
h0<=cnt0;
end process;
end hour_arc;
5.扫描模块程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity SELTIME is
port(
clk:in std_logic;
sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0);
daout:out std_logic_vector(3 downto 0);
sel:out std_logic_vector(2 downto 0));
end SELTIME;
architecture fun of SELTIME is
signal count:std_logic_vector(2 downto 0);
begin
sel<=count;
process(clk)
begin
if(clk'event and clk='1') then
if(count>="101") then
count<="000";
else
count<=count+1;
end if;
end if;
case count is
when"000"=>daout<= sec0;
when"001"=>daout<= sec1;
when"010"=>daout<= min0;
when"011"=>daout<= min1;
when"100"=>daout<=h0;
when others =>daout<=h1;
end case;
end process;
end fun;
6.显示模块程序
library ieee;
use ieee.std_logic_1164.all;
entity DISPLAY is
port(d:in std_logic_vector(3 downto 0);
q:out std_logic_vector(6 downto 0));
end DISPLAY;
architecture disp_are of DISPLAY is
begin
process(d)
begin
case d is
when"0000" =>q<="0111111";
when"0001" =>q<="0000110";
when"0010" =>q<="1011011";
when"0011" =>q<="1001111";
when"0100" =>q<="1100110";
when"0101" =>q<="1101101";
when"0110" =>q<="1111101";
when"0111" =>q<="0100111";
when"1000" =>q<="1111111";
when others =>q<="1101111";
end case;
end process;
end disp_are;
7.定时闹钟模块程序
library ieee;
use ieee.std_logic_1164.all;
entity ALERT is
port(m1,m0,s1,s0:in std_logic_vector(3 downto 0);
clk:in std_logic;
q500,qlk:out std_logic);
end ALERT;
architecture sss_arc of ALERT is
begin
process(clk)
begin
if clk'event and clk='1' then
if m1="0101" and m0="1001" and s1="0101" then
if s0="0001" or s0="0011" or s0="0101" or s0="0111" then
q500<='1';
else
q500<='0';
end if;
end if;
if m1="0101" and m0="1001" and s1="0101" and s0="1001" then
qlk<='1';
else
qlk<='0';
end if;
end if;
end process;
end sss_arc;
程序启动，校时，校分使能输入
校对用的加减输入
时分秒显示输出
根据CLK进行“秒”的累加，逐次进行进位判断。“时”就根据“分”的进位判断。这是数字电路连线的思路啦。呵呵
还可以参考一下这个，要方便的多
VHDL数字时钟完整程序代码(要求要有元件例化,并且有按键消抖),谢谢啦啦...
8、整点报时及闹时：模块图如图15。在59分51秒、53秒、55秒、57秒给扬声器赋以低音512Hz信号,在59分59秒给扬声器赋以高音1024Hz信号,音响持续1秒钟,在1024Hz音响结束时刻为整点。当系统时间与闹铃时间相同时给扬声器赋以高音1024Hz信号。闹时时间为一分钟。图15 程序如下：library IEEE;use IEEE....
vhdl数字钟的代码
USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;entity xsecond is port (clk:in std_logic;clkset:in std_logic;setmin:in std_logic;reset:in std_logic;secout:out std_logic_vector(6 downto 0);enmin:out std_logic );end xsecond;ar...
数字钟vhdl程序代码源
end disp_are;7.定时闹钟模块程序 library ieee;use ieee.std_logic_1164.all;entity ALERT isport(m1,m0,s1,s0:in std_logic_vector(3 downto 0); clk:in std_logic; q500,qlk:out std_logic);end ALERT;architecture sss_arc of ALERT is begin process(clk) begin if clk'event and clk='1' t...
时钟VHDL
---VHDL源代码。 文件名： digital_clock.vhd library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity digital_clock is port(reset,clk: in std_logic;hour,minitue,second: out std_logic_vector(7 downto 0);hex0,hex1,hex2,hex3,hex4,hex5: out std_l...
基于vhdl语言设计一个数字钟 高手帮帮忙啊
采用VHDL语言输入方式,以时钟clk,清零信号clr以及暂停信号STOP为进程敏感变量,程序如下:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity MINSECONDb isport(clk,clrm,stop:in std_logic;---时钟\/清零信号 secm1,secm0:out std_logic_vector(3 downto 0);---秒高位\/低位...
求一个数字钟vhdl程序: 设计一个能显示1\/10秒、秒、分、时的12小时数 ...
1。首先是系统CLK的选择，由于你要显示1\/10秒，也就是100ms为一个基本单位，这样你的时钟频率最低不能小于10Hz。2。写几个计数器。1。第一个计数器用于1\/10秒到1秒之间的技术，计10个清0，输出一个控制信号a；2。第二个计数器用于1秒到1分之间的技术，每来一个a，计数一次；计数到60，清0...
基于VHDL语言的自动打铃数字钟设计
诸如定时自动报警、按时自动打铃、时间程序自动控制、定时广播、定时启闭电路、定时开关烘箱、通断动力设备,甚至各种定时电气的自动启用等,所有这些,都是以钟表数字化为基础的。因此,研究数字钟及扩大其应用,有着非常现实的意义。 (二)论文的研究内容和结构安排 本系统采用石英晶体振荡器、分频器、计数器、显示器和...
求高手帮忙用vhdl编一个2,4,8,16分频程序
这是对时钟进行10分频的VHDL代码，2,4,8,16分频原理与其相同。entity clk_div is port (clk_in :in std_logic;clk_out:out std_logic);end clk_div;architecture Behavioral of clk_div is signal cnt:integer range 1 to 10;signal clk_temp:std_logic:='0';begin process (clk_in,cnt)...
基于VHDL的数字时钟设计 用VHDL设计EDA数字钟 能显示年月日 时分秒 能...
template class TreeNode{ public:T data;int index;int active;TreeNode & operator=(TreeNode & treenode){ this->data=treenode.data;this->index=treenode.index;this->active=treenode.active;return *this;} };
求一个数字跑表VHDL程序,(时钟输入(CLK)、复位(CLR)和启动\/暂停(PAUSE...
USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY PAOBIAO IS PORT(CLK,CLR,PAUSE:IN STD_LOGIC;cs1:OUT std_logic_vector(6 DOWNTO 0);cs2:OUT std_logic_vector(6 DOWNTO 0);s1:OUT std_logic_vector(6 DOWNTO 0);s2:OUT std_logic_vector(6 DOWNTO 0);m1:OUT std_logic_vector(6 DOWNTO 0...
濯惠孚顺： 下面是笔者写过的一个液晶显示时钟改成的数码管显示时钟,已经通过编译,不过没有硬件实践,(液晶显示通过了硬件验证).你可以验证一下!另带有时间调整功能,如不需要可删除. (时钟频率可自行修改成1s)library ieee; use ieee.std...
玉泉区13437701322： 高分求 基于VHDL语言设计的数字时钟 - ？
濯惠孚顺： -------------------程序(.vhd文件)如下--------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ...
玉泉区13437701322： 用VHDL语言设计一个电子时钟 - ？
濯惠孚顺： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity shuzizhong is port(clk,,clk1,set,change,s1,s2,s3:in std_logic; second1,second2,minite1,minite2,hour1,hour2:out std_logic_vector(3 downto 0); Light:out std_logic_vector...
玉泉区13437701322： VHDL电子时钟设计 - ？
濯惠孚顺： 基于CPLD的VHDL语言数字钟(含秒表)设计 利用一块芯片完成除时钟源、按键、扬声器和显示器(数码管)之外的所有数字电路功能.所有数字逻辑功能都在CPLD器件上用VHDL语言实现.这样设计具有...
玉泉区13437701322： 急!!!在QUARTUS II中使用VHDL语言设计分为时、分、秒三个模块的数字钟 - ？
濯惠孚顺： 这个跟三个VHDL文件没有关系.你建立波形文件后需要再次编译,如果没有成功继续编译.还是只有一个模块,你把你总的实现功能,就是用到元件例化的那个vhdl设置为顶层文件试一试,再编译一次.
玉泉区13437701322： 用VHDL语言写数字钟,要有整点报时的 - ？
濯惠孚顺： a.秒计数器设计(xsecond)<br>LIBRARY IEEE;<br> USE IEEE.STD_LOGIC_1164.ALL;<br> USE IEEE.STD_LOGIC_UNSIGNED.ALL;<br> USE IEEE.STD_LOGIC_ARITH.ALL;<br> entity xsecond is<br> port (clk:in std_logic;<br> clkset:in std_...
玉泉区13437701322： VHDL编程产生一个100kHz的时钟信号？
濯惠孚顺： 你的硬件系统中总要有一个振荡器作为主时钟信号的,FPGA自己是振荡不起来的.只要有了主时钟信号,你就可以通过设置FPGA中的PLL产生一个100kHz的时钟信号了.也可以自己描述一个分频器对主时钟信号进行分频,从而产生100kHz的时钟信号.
玉泉区13437701322： Xilinx 的VHDL设计时钟 - ？
濯惠孚顺： 我最近没时间给你们写代码了;不好意思!不过我可以给你提点意见;24小时制,就是用计数器来做.两个按键无非就是一个边沿触发,当边沿触发有效时就修改时间.然后在设定一个确定键.当时间到设定的脑中只是,设计alam=1进行闹钟驱动
玉泉区13437701322： 秒表的VHDL语言设计程序! - ？
濯惠孚顺： 用vhdl设计秒表全功略!根据要求, 秒表的设计要有三个输入端:runstop,rst和clk. runstop是开关, 按一下开始计时, 再按一下停止计时, 显示时间. 可以使用一个T触发器来实现. 当我们把T触发器的T端接高电平时, 它将实现翻转功能. 然后用...
玉泉区13437701322： 利用VHDL语言设计一个十六进制计数器? - ？
濯惠孚顺： -- A asynchronous reset;;enable up; 8421BCD counter-- module=60;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY cntm60v IS PORT (en: ...
