用VHDL语言实现四人智力竞赛抢答器的设计,高分寻高人解答

作者&投稿:何师 (若有异议请与网页底部的电邮联系)
用VHDL语言实现四人智力竞赛抢答器的设计,高分寻高人解答~

专业 生产 销售 电子抢答器 电脑抢答器 www.shbupin.com

我最近也在做呢

四路抢答 四路控制

做好了 咱交流

各模块VHDL源代码
1、抢答鉴别模块FENG的VHDL源程序
--feng.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FENG IS
PORT(CP,CLR:IN STD_LOGIC;
Q :OUT STD_LOGIC);
END FENG;
ARCHITECTURE FENG_ARC OF FENG IS
BEGIN
PROCESS(CP,CLR)
BEGIN
IF CLR='0'THEN
Q<='0';
ELSIF CP'EVENT AND CP='0'THEN
Q<='1';
END IF;
END PROCESS;
END FENG_ARC;

2、片选信号产生模块SEL的VHDL源程序
--sel.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SEL IS
PORT(CLK:IN STD_LOGIC;
a:OUT INTEGER RANGE 0 TO 7);
END SEL;
ARCHITECTURE SEL_ARC OF SEL IS 片选信号产生模块SEL
BEGIN
PROCESS(CLK)
VARIABLE AA:INTEGER RANGE 0 TO 7;
BEGIN
IF CLK'EVENT AND CLK='1'THEN
AA:=AA+1;
END IF;
A<=AA;
END PROCESS;
END SEL_ARC;

3、锁存器模块LOCKB的VHDL源程序
-lockb.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY LOCKB IS
PORT(D1,D2,D3,D4:IN STD_LOGIC;
CLK,CLR:IN STD_LOGIC;
Q1,Q2,Q3,Q4,ALM:OUT STD_LOGIC);
END LOCKB;
ARCHITECTURE LOCK_ARC OF LOCKB IS
BEGIN
PROCESS(CLK)
BEGIN
IF CLR='0'THEN
Q1<='0';
Q2<='0';
Q3<='0';
Q4<='0';
ALM<='0'; 模块LOCKB
ELSIF CLK'EVENT AND CLK='1'THEN
Q1<=D1;
Q2<=D2;
Q3<=D3;
Q4<=D4;
ALM<='1';
END IF;
END PROCESS;
END LOCK_ARC;

4、转换模块CH41A的VHDL源程序
--ch41a..vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CH41A IS
PORT(D1,D2,D3,D4:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END CH41A;
ARCHITECTURE CH41_ARC OF CH41A IS 转换模块CH41A
BEGIN
PROCESS(D1,D2,D3,D4)
VARIABLE TMP:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
TMP:=D1&D2&D3&D4;
CASE TMP IS
WHEN "0111"=>Q<="0001";
WHEN "1011"=>Q<="0010";
WHEN "1101"=>Q<="0011";
WHEN "1110"=>Q<="0100";
WHEN OTHERS=>Q<="1111";
END CASE;
END PROCESS;
END CH41_ARC;

5、3选1模块CH31A的VHDL源程序
--ch31a.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CH31A IS
PORT(SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
D1,D2,D3:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END CH31A;
ARCHITECTURE CH31_ARC OF CH31A IS
BEGIN
PROCESS(SEL,D1,D2,D3)
BEGIN
CASE SEL IS
WHEN "000"=>Q<=D1;
WHEN "001"=>Q<=D2;
WHEN "111"=>Q<=D3;
WHEN OTHERS=>Q<="1111";
END CASE;
END PROCESS;
END CH31_ARC;

6、倒计时模块COUNT的VHDL源程序
倒计时模块COUNT如图16-7所示,该模块实现答题时间的倒计时,在计满100s后送出声音提示。
--count.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT IS
PORT(CLK,EN:IN STD_LOGIC; 倒计时 模块COUNT
H,L:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SOUND:OUT STD_LOGIC);
END COUNT;
ARCHITECTURE COUNT_ARC OF COUNT IS
BEGIN
PROCESS(CLK,EN)
VARIABLE HH,LL:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF CLK'EVENT AND CLK='1'THEN
IF EN='1'THEN
IF LL=0 AND HH=0 THEN
SOUND<='1';
ELSIF LL=0 THEN
LL:="1001";
HH:=HH-1;
ELSE
LL:=LL-1;
END IF;
ELSE
SOUND<='0';
HH:="1001";
LL:="1001";
END IF;
END IF;
H<=HH;
L<=LL;
END PROCESS;
END COUNT_ARC;

7、显示译码模块DISP的VHDL源程序
--disp.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DISP IS 显示译码模块DISP
PORT(D:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Q:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END DISP;
ARCHITECTURE DISP_ARC OF DISP IS
BEGIN
PROCESS(D)
BEGIN
CASE D IS
WHEN"0000"=>Q<="0111111";
WHEN"0001"=>Q<="0000110";
WHEN"0010"=>Q<="1011011";
WHEN"0011"=>Q<="1001111";
WHEN"0100"=>Q<="1100110";
WHEN"0101"=>Q<="1101101";
WHEN"0110"=>Q<="1111101";
WHEN"0111"=>Q<="0100111";
WHEN"1000"=>Q<="1111111";
WHEN"1001"=>Q<="1101111";
WHEN OTHERS=>Q<="0000000";
END CASE;
END PROCESS;
END DISP_ARC;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------
entity exp19 is
port( Clk : in std_logic; --时钟信号
Rst : in std_logic; --复位信号
Kr : in std_logic_vector(3 downto 0); --键盘行
Kc : buffer std_logic_vector(3 downto 0); --键盘列
SPK : out std_logic; --扬声器输出
KEY_State : out std_logic; --按键指示
Door : buffer std_logic; --门状态
Display : out std_logic_vector(7 downto 0); --七段码管显示
SEG_SEL : buffer std_logic_vector(2 downto 0)); --七段码管片选
end exp19;
--------------------------------------------------------------------
architecture behave of exp19 is

signal keyr,keyc : std_logic_vector(3 downto 0);
signal kcount : std_logic_vector(2 downto 0);
signal kflag1,kflag2 : std_logic;
signal buff1,buff2,buff3,buff4,buff5,buff6 : integer range 0 to 15;
signal push_num : integer range 0 to 15; --按键次数

signal Disp_Temp : integer range 0 to 15;
signal Disp_Decode : std_logic_vector(7 downto 0);
signal SEC1,SEC10 : integer range 0 to 9;

signal Clk_Count1 : std_logic_vector(3 downto 0); --1KHz时钟分频计数器
signal Clk_Count2 : std_logic_vector(9 downto 0); --2Hz时钟分频计数器
signal Clk1KHz : std_logic;
signal Clk2Hz : std_logic;
signal Clk1Hz : std_logic;

signal Error_Num : integer range 0 to 3;
signal Error_Flag : std_logic;
signal Error_Count : std_logic_vector(2 downto 0);

signal Music_Count : std_logic_vector(2 downto 0);

begin
process(Clk)
begin
if(Clk'event and Clk='1') then
if(Clk_Count1<10) then
Clk_Count1<=Clk_Count1+1;
else
Clk_Count1<="0001";
end if;
end if;
end process;
Clk1KHz<=Clk_Count1(2);

process(Clk1KHz)
begin
if(Clk1KHz'event and Clk1KHz='1') then
if(Clk_Count2<1000) then
Clk_Count2<=Clk_Count2+1;
else
Clk_Count2<="0000000001";
end if;
end if;
end process;
Clk2Hz<=Clk_Count2(9);

process(Clk2Hz)
begin
if(Clk2Hz'event and Clk2Hz='1') then
Clk1Hz<=not Clk1Hz;
end if;
end process;

process(Clk1KHz) --扫描键盘
begin
if(Clk1KHz'event and Clk1KHz='1') then
if(Kr="1111") then
kflag1<='0';
kcount<=kcount+1;
if(kcount=0) then
kc<="1110";
elsif(kcount=1) then
kc<="1101";
elsif(kcount=2) then
kc<="1011";
else
kc<="0111";
end if;
else
kflag1<='1';
keyr<=Kr;
keyc<=Kc;
end if;
kflag2<=kflag1;
end if;
end process;
KEY_State<=kflag1;

process(Clk1KHz,Rst) --扫描键盘
begin
if(Rst='0') then
push_num<=0;
elsif(Clk1KHz'event and Clk1KHz='1') then
if(push_num=6) then
push_num<=0;
elsif(kflag1='0' and kflag2='1') then
push_num<=push_num+1;
end if;
end if;
end process;

process(Clk1KHz,Rst) --密码校验
begin
if(Rst='0') then
Door<='0';
Error_Num<=0;
Error_Flag<='0';
elsif(Clk1KHz'event and Clk1KHz='1') then
if(push_num=5 and Error_Num<3) then
--修改此处的值可修改门的密码,此处密码为123456
if(buff1=1 and buff2=2 and buff3=3 and buff4=4 and buff5=5 and buff6=6) then
Door<='1';
else
Door<='0';
end if;
elsif(push_num=6 and Error_Num<3) then
if(Door='0') then
Error_Flag<='1';
Error_Num<=Error_Num+1;
else
Error_Flag<='0';
Error_Num<=0;
end if;
elsif(Error_Count=4) then
Error_Flag<='0';
elsif(Error_Flag='1') then
Door<=not Error_Count(0);
end if;
end if;
end process;

process(Clk2Hz,Rst)
begin
if(Rst='0' or Error_Flag<='0') then
Error_Count<="000";
elsif(Clk2Hz'event and Clk2Hz='1' and Error_Flag<='1') then
Error_Count<=Error_Count+1;
end if;
end process;

process(Clk) --报警声音分频
begin
if(Clk'event and Clk='1') then
Music_Count<=Music_Count+1;
end if;
end process;
process(Clk) --超出错误次数,开始报警
begin
if(Error_Num>=3) then
if(Clk1Hz='1') then
SPK<=Music_Count(2);
else
SPK<=Music_Count(1);
end if;
end if;
end process;

process(Clk1KHz,Rst) --显示右移
begin
if(Rst='0' or push_num=0) then --复位时,全灭
buff1<=15;
buff2<=15;
buff3<=15;
buff4<=15;
buff5<=15;
elsif(Clk1KHz'event and Clk1KHz='1') then
if(kflag1='1' and kflag2='0' and (((keyr="1110" or keyr="1011")and keyc/="0111")or keyr="1101")) then
buff1<=buff2;
buff2<=buff3;
buff3<=buff4;
buff4<=buff5;
buff5<=buff6;
end if;
end if;
end process;
process(Clk1KHz,Rst) -- 获取键值
begin
if(Rst='0' or push_num=6) then --全灭
buff6<=15;
elsif(Clk1KHz'event and Clk1KHz='1') then
if(kflag1='1' and kflag2='0') then
if(keyr="1110") then
case keyc is
when "1110"=>buff6<=1;
when "1101"=>buff6<=4;
when "1011"=>buff6<=7;
when others=>buff6<=buff6; --no change
end case;
elsif(keyr="1101") then
case keyc is
when "1110"=>buff6<=2;
when "1101"=>buff6<=5;
when "1011"=>buff6<=8;
when "0111"=>buff6<=0;
when others=>buff6<=buff6; --no change
end case;
elsif(keyr="1011") then
case keyc is
when "1110"=>buff6<=3;
when "1101"=>buff6<=6;
when "1011"=>buff6<=9;
when others=>buff6<=buff6; --no change
end case;
end if;
end if;
end if;
end process;
process(SEG_SEL)
begin
case (SEG_SEL+1) is
when "000"=>Disp_Temp<=10; --'-'
when "001"=>Disp_Temp<=buff1;
when "010"=>Disp_Temp<=buff2;
when "011"=>Disp_Temp<=buff3;
when "100"=>Disp_Temp<=buff4;
when "101"=>Disp_Temp<=buff5;
when "110"=>Disp_Temp<=buff6;
when "111"=>Disp_Temp<=10; --'1'
end case;
end process;

process(Clk)
begin
if(Clk'event and Clk='1') then --扫描累加
SEG_SEL<=SEG_SEL+1;
Display<=Disp_Decode;
end if;
end process;
process(Disp_Temp) --显示转换
begin
case Disp_Temp is
when 0=>Disp_Decode<="00111111"; --'0'
when 1=>Disp_Decode<="00000110"; --'1'
when 2=>Disp_Decode<="01011011"; --'2'
when 3=>Disp_Decode<="01001111"; --'3'
when 4=>Disp_Decode<="01100110"; --'4'
when 5=>Disp_Decode<="01101101"; --'5'
when 6=>Disp_Decode<="01111101"; --'6'
when 7=>Disp_Decode<="00000111"; --'7'
when 8=>Disp_Decode<="01111111"; --'8'
when 9=>Disp_Decode<="01101111"; --'9'
when 10=>Disp_Decode<="01000000"; --'-'
when others=>Disp_Decode<="00000000"; --全灭
end case;
end process;

end behave;

自己不去做,叫人做永远都不会。只有动手过,才有其意义

哦....这样啊

希望 你找到答案


如何用VHDL语言设计一个4位二进制数可预置可逆计的计数器???急求...
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;entity counter4 is port (clk : in std_logic;load : in std_logic;clr : in std_logic;up_down: in std_logic;DIN : in std_logic_vector(3 downto 0);DOUT : out std_logic_vect...

现代电子技术:VHDL与数字系统设计中,vhdl实验如何实现基本门电路描述...
第1章,VHDL语言基础:1.1 概述了VHDL编程的基础概念。1.2 VHDL程序结构包括: 1.2.1 基本结构,描述程序的基本组织。 1.2.2 实体(Entity),定义系统的行为。 1.2.3 结构体(Architecture),详细设计实体的行为。 1.2.4 配置(Configuration),设置实体的实例化。 1.3 设计...

用VHDL语言设计一个四位二进制数循环左移一位器的具体写法,谢谢了...
没当do为1时循环左移一位:library IEEE;use IEEE.std_logic_1164.all;use IEEE.numeric_std.all;use IEEE.std_logic_unsigned.all;entity txt is port (clk:in std_logic;do:in std_logic;putout:out std_logic_vector(3 downto 0));end entity;architecture behav of txt is signal tmp:...

四位移位寄存器用vhdl语言设计?
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ls194 IS PORT(d :IN STD_LOGIC_VECTOR(0 TO 3);cr,sr,sl,s1,s0:IN STD_LOGIC;cp :IN STD_LOGIC;q :OUT STD_LOGIC_VECTOR(0 TO 3));END ls194;ARCHITECTURE rtl OF ls194 IS SIGNAL pcx:STD_LOGIC_VECTOR(0 TO 3);BE...

用VHDL语言设计一个具有清零,使能,置数的4位二进制加减法计数器的源...
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;entity counter4 is port (clk : in std_logic;load : in std_logic;clr : in std_logic;up_down: in std_logic;DIN : in std_logic_vector(3 downto 0);DOUT : out std_logic_vect...

VHDL语言VHDL简介
VHDL,全称为Very-High-Speed Integrated Circuit Hardware Description Language,诞生于1982年,标志着硬件描述语言发展的一个重要里程碑。1987年,IEEE和美国国防部正式将其确立为标准,以支持高速集成电路的设计和描述。VHDL的核心功能在于它能够精确地刻画数字系统的结构、行为和功能,包括其接口。它的语言...

如何实现用EDA的VHDL语言四个开关一盏灯
看看使用状态机能不能实现。

一共四个状态00,01,10,11 。用VHDL语言实现01,11触发蜂鸣器响
LIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL;ENTITY speaker IS PORT(clock:IN Std_logic;speaker_out:OUT Std_Logic);END speaker;ARCHITECTURE behave OF speaker IS SIGNAL state: std_logic_vector(1 downto 0);BEGIN PROCESS(clock)BEGIN IF rising_edge(clock) THEN CASE state IS WHEN "00"...

在Quartus II下使用VHDL语言编程实现模块间相互调用的步骤
在QuartusII下使用VHDL语言编程实现元件例化为了有效应用现有开发资源,往往需要实现模块间的调用。即实现元件的声明和例化。作为示例,这里建立了两个模块:一个是两个1位数相加的半加器h_adder,另一个是两个2位数相加的全加器twobit_addr,twobit_addr需要调用h_dder。步骤如下:第一步:首先在D:\\...

用D触发器或VHDL语言设计一个计数器。其计数顺序为4,5,1,3,2,6,4。
直接用译码的方法,FPGA就是这样工作的 比如就是设计一个加到6清0的计数器A,一个输出B,如果A为0,B就输出4,如果A为1,B就输出5,以此类推,如if(A=0),B=4 if(A=1),B=5 if(A=2),B=1 if(A=3),B=3 if(A=4),B=2 ......

庐阳区13852102069: 用VHDL语言实现四人智力竞赛抢答器的设计,高分寻高人解答 -
漳晓加立: 各模块VHDL源代码1、抢答鉴别模块FENG的VHDL源程序--feng.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FENG IS PORT(CP,CLR:IN STD_LOGIC; Q :OUT STD_LOGIC); END FENG; ARCHITECTURE FENG_ARC OF ...

庐阳区13852102069: 急求四人抢答器vhdl语言编的 !!高手速来帮忙!! -
漳晓加立: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;-------------------------------------------------------------------- entity exp5 is port( S1,S2,S3,S4 : in std_logic; --输入:表示4个人 S5 : in std_logic; --主持人...

庐阳区13852102069: 用vhdl或verilog设计四人竞赛抢答器 -
漳晓加立: 我可以给你啊,用数字电路做的,你移植到CPLD上就可以了.报警电路,你用CPLD做个频率就好了,很简单的.延时电路也是一样的.

庐阳区13852102069: 设计数字式竞赛抢答器,用VHDL语言描述,用QuartusII工具编译和综合 -
漳晓加立: 7位抢答器设计:LIBRARY IEEE;USE IEEE.Std_logic_1164.ALL;ENTITY Responder IS -- 实体声明 PORT(Start:IN Std_logic; -- 端口声明 Key:IN Std_logic_Vector(7 DOWNTO 1); Led:OUT Std_logic_Vector(7 DOWNTO 1));END Responder;...

庐阳区13852102069: 求quartus2 的 设计实例
漳晓加立:EDA中用VHDL语言设计五人抢答器 1.电路设置有5个抢答按钮A~E,开始抢答控制按钮Start,以及复位按钮RST 2.抢答前或复位时数码管显示为“0”,抢答完成后则显示抢答者的编号“1”~“5” library ieee; use ieee.std_logic_1164.all; use ...

庐阳区13852102069: 描述下本电路是如何实现四路输入抢答功能的? -
漳晓加立: vvc:设计一个4人参加的智力竞赛抢答计时器1:当有某一个参赛者下按抢答开关时.相应显示等亮.并伴有声响;且此时抢答器不再接受其他输入信号;2:电路具有回答问题时间控制功能.要求回答问题小于等于100s(显示0——99s)....

庐阳区13852102069: 智力竞赛抢答器设计
漳晓加立: 去看看吧 希望对你有帮助http://www.lm.gov.cn/gb/training/2009-02/03/content_275694.htm

庐阳区13852102069: 如何在基于VHDL设计的抢答器中加入语音功能,比如在强大倒数时能语音数秒,语音喊开始等功能 -
漳晓加立: 你的抢答器肯定是由许多的计时电路构成的,你可以加一个蜂鸣器,用一定频率的时钟来使蜂鸣器工作,一般都是用256HZ.先说读秒,把你的读秒时钟脉冲(CLK)和蜂鸣器的驱动时钟用一个与门接在一起再送给蜂鸣器,这样蜂鸣器就会在CLK高电平期间发声,低电平停止工作,实现了读秒.报警报错,可以再你的计数末尾输出一个高电平脉冲,作为错误或警报信号给蜂鸣器就可以了.

庐阳区13852102069: 数字电子技术课程设计:八路智力竞赛抢答器的仿真电路图 -
漳晓加立: 下面这个图是五路抢答器的,按照同样的道理多加三个就成了八路抢答器 另一电路 基于4511的八路抢答器:仿真电路3:

庐阳区13852102069: 数字电路设计:六人抢答器 -
漳晓加立: 用数字电路实现抢答器 一、设计目标 设计一个带有用户选手按下后,其他用户选手按下无效,同时,响警报、显示是谁按下的.由主持人开关复位的抢答器. 二、 基本功能 我设计的抢答器有如下功能:有人按下时,显示是谁按下的.同时,其...

本站内容来自于网友发表,不代表本站立场,仅表示其个人看法,不对其真实性、正确性、有效性作任何的担保
相关事宜请发邮件给我们
© 星空见康网