VHDL电子时钟设计

用VHDL语言设计一个电子时钟~

秒计时模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity second is
port (clk,reset,setmin:in std_logic;
enmin:out std_logic;
dh:buffer std_logic_vector (3 downto 0);
dl:buffer std_logic_vector (3 downto 0);
end;
architecture beha of second is
begin
process(clk,reset,setmin)
bigin
if setmin='0' then
enmin<=clk;
elsif dl="1001" and dh="0101" then
enmin<='0';
else
enmin<='1';
end if;
if reset='0' then
dh<="0000";
dl<="0000";
elsif (clk'event and clk='1') then
if dl=9 then
dl<="0000";
if dh=5 then
dh<="0000";
else
dh<=dh+1;
end if;
else
dl<=dl+1;
end if;
end if;
end process;
end;
分计时模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity minute is
port (clk,clk1,reset,sethour:in std_logic;
enhour:out std_logic;
dh:buffer std_logic_vector (3 downto 0);
dl:buffer std_logic_vector (3 downto 0);
end;
architecture beha of minute is
begin
process (clk,clk1,reset,sethour)
begin
if sethour='0' then
enhour<=clk1;
elsif dl="1001" and dh="0101" then
enhour<='0';
else
enhour<='1';
end if;
if reset='0' then
dh<="0000";
dl<="0000";
elsif (clk'event and clk='1') then
if dl=9 then
dl<="0000";
if dh=5 then
dh<="0000";
else
dh<=dh+1;
end if;
else
dl<=dl+1;
end if;
end if;
end process;
end;
时计时模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hour is
port (clk,reset:in std_logic;
dh:buffer std_logic_vector (3 downto 0);
dl:buffer std_logic_vector (3 downto 0);
end;
architecture beha of hour is
begin
process (clk,reset)
begin
if reset='0' then
dh<="0000";
dl<="0000";
elsif (clk'event and clk='1') then
if dh="0010" and dl="0011" then
dl<="0000";
dh<="0000";
elsif dl=9 then
dl<="0000";
if dh=2 then
dh<="0000";
else
dh<=dh+1;
end if;
end if;
end process;
end;
轮流显示模块
library ieee;
use ieee.std_logic_1164.all;
entity lunliu1 is
port (sech,secl,minh,minl,hourh,hourl:in std_logic_vector (3 downto 0);
clk:in std_logic;
q:buffer std_logic_vector (5 downto 0);
dout:out std_logic_vector (3 downto 0));
end;
architecture beha of lunliu1 is
signal qin: integer range 5 downto 0;
begin
process (clk)
begin
if (clk'event and clk='1') then
if qin>=5 then
qin<=0;
else
qin<=qin+1;
end if;
end if;
if qin=0 then
dout<=secl (3 downto 0);
q<="111110";
elsif qin=1 then
dout<=sech (3 downto 0);
q<="111101";
elsif qin=2 then
dout<=minl (3 downto 0);
q<="111011";
elsif qin=3 then
dout<=minh (3 downto 0);
q<="110111";
elsif qin=4 then
dout<=hourl (3 downto 0);
q<="101111";
elsif qin=5 then
dout<=hourh (3 downto 0);
q<="011111";
end if;
end process;
end;
译码模块
library ieee;
use ieee.std_logic_1164.all;
entity xianshi is
port (num:in std_logic_vector (3 downto 0);
led8:out std_logic_vector (7 downto 0));
end;
architecture beha of xianshi is
begin
process (num)
begin
case num is
when "0000"=>led8<="11000000";
when "0001"=>led8<="11111001";
when "0010"=>led8<="10100100";
when "0011"=>led8<="10110000";
when "0100"=>led8<="10011001";
when "0101"=>led8<="10010010";
when "0110"=>led8<="10000010";
when "0111"=>led8<="11111000";
when "1000"=>led8<="10000000";
when "1001"=>led8<="10010000";
when others=>null;
end case;
end process;
end;
报时信号产生模块
library ieee;
use ieee.std_logic_1164.all;
entity speak is
port (clk,hour:in std_logic;
speak:out std_logic);
end;
architecture beha of speak is
begin
process (hour)
begin
if (hour'event and hour=1) then
speak<=clk;
end if;
end process;
end;

***********百分秒*************************
entity count100 is
Port ( shift_temp,clk: in STD_LOGIC;
q:out std_logic_vector(7 downto 0);
co:out std_logic);
end count100;

architecture Behavioral of count100 is
signal temp:std_logic_vector(7 downto 0):=(others=>'0');
begin
process(clk)
begin
if clk'event and clk='1' then
if temp(3 downto 0)=9 then
if temp(7 downto 4)=9 then
temp'0');co<='1';
else temp(7 downto 4)'0');co<='0';end if;
else temp(3 downto 0)<=temp(3 downto 0)+1;co<='0';end if;
end if;
end process;
q<=temp;
end Behavioral;

****************************秒，分*******************
entity count60 is
Port ( shift_temp,key_m,clk: in STD_LOGIC;
q:out std_logic_vector(7 downto 0);
co:out std_logic);
end entity;
architecture Behavioral of count60 is
signal temp:std_logic_vector(7 downto 0):=(others=>'0');
signal temp_clk,temp_co:std_logic;
begin
process(shift_temp)
begin
if shift_temp='1' then temp_clk<=key_m;co<='0';
else temp_clk<=clk;co<=temp_co;
end if;
end process;
process(temp_clk)
begin
if temp_clk'event and temp_clk='1' then
if temp(3 downto 0)=9 then
if temp(7 downto 4)=5 then
temp'0');temp_co<='1';
else temp(7 downto 4)'0');temp_co<='0';end if;
else temp(3 downto 0)<=temp(3 downto 0)+1;temp_co<='0';end if;
end if;
end process;
q<=temp;
end Behavioral;

******************************小时**********************************
entity count24 is
Port ( shift_temp,key_m,clk: in STD_LOGIC;
q:out std_logic_vector(7 downto 0));
end count24;

architecture Behavioral of count24 is
signal temp_q:std_logic_vector(7 downto 0):=(others=>'0');
signal temp:std_logic_vector(4 downto 0);
signal temp_clk:std_logic;
begin
process(shift_temp)
begin
if shift_temp='1' then temp_clk<=key_m;
else temp_clk<=clk;
end if;
end process;
process(temp_clk)
begin
if temp_clk'event and temp_clk='1' then
if temp="10111" then temp'0');
elsif temp="01001" or temp="10011" then
temp_q(3 downto 0)<="0000";temp_q(7 downto 4)<=temp_q(7 downto 4)+1;temp<=temp+1;
else temp_q(3 downto 0)<=temp_q(3 downto 0)+1;temp<=temp+1;
end if;
end if;
end process;
q<=temp_q;
end Behavioral;
************************分频****************************
entity clock is
Port ( clk : in STD_LOGIC;
clk_out:out std_logic_vector(3 downto 0));
end clock;

architecture Behavioral of clock is
signal temp_clk:std_logic_vector(3 downto 0);
signal temp0,temp1,temp2,temp3:std_logic_vector(24 downto 0):=(others=>'0');
begin
process(clk)
begin
if clk'event and clk='0' then
if temp0=24999999 then
temp_clk(0)'0');
else temp0<=temp0+1;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk='0' then
if temp1=249999 then
temp_clk(1)'0');
else temp1<=temp1+1;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk='0' then
if temp2=124999 then
temp_clk(2)'0');
else temp2<=temp2+1;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk='0' then
if temp3=249 then
temp_clk(3)'0');
else temp3<=temp3+1;
end if;
end if;
end process;
clk_out<=temp_clk;
end Behavioral;
***********************调时闪烁**********************
entity clos is
Port (clk:in std_logic;
q : in STD_LOGIC_vector(2 downto 0);
q_out:out std_logic_vector(5 downto 0));
end clos;

architecture Behavioral of clos is
signal temp:std_logic_vector(5 downto 0);
begin
process(q)
begin
case q is
when "000"=>temp'0');
when "001"=>temp(0)<=clk;temp(1)<=clk;temp(5 downto 2)<="0000";
when "010"=>temp(3)<=clk;temp(2)<=clk;temp(5 downto 4)<="00";temp(1 downto 0)<="00";
when "100"=>temp(5)<=clk;temp(4)<=clk;temp(3 downto 0)<="0000";
when others=>null;
end case;
end process;
q_out<=temp;
end Behavioral;
*************************去抖动***********************************
entity kicker is
Port ( clk,din : in STD_LOGIC;
d_out:out std_logic);
end kicker;

architecture Behavioral of kicker is
signal x,y,d:std_logic:='0';
begin
process(clk)
begin
if clk'event and clk='1'
then x<=din;y<=x;d<=x and y;
end if;
end process;
d_out<=d;
end Behavioral;
******************调时控制信号************************
entity shift is
Port ( key_in : in STD_LOGIC;
shift_out: out std_logic_vector(3 downto 0));
end shift;

architecture Behavioral of shift is
signal data:std_logic_vector(3 downto 0):="0001";
begin
process(key_in)
begin
if key_in'event and key_in='1' then
data(2 downto 0)<=data(3 downto 1);
data(3)<=data(0);
end if;
end process;
shift_out(3 downto 0)<=data(3 downto 0);
end Behavioral;
*****************32位数据输出文件******************
entity count32 is
Port ( m,s,clk: in STD_LOGIC;
data:out std_logic_vector(31 downto 0);
close:out std_logic_vector(2 downto 0));
end count32;

architecture Behavioral of count32 is
component count100
Port ( shift_temp,clk: in STD_LOGIC;
q:out std_logic_vector(7 downto 0);
co:out std_logic);
end component;
component count60
Port ( shift_temp,key_m,clk: in STD_LOGIC;
q:out std_logic_vector(7 downto 0);
co:out std_logic);
end component;
component count24
Port ( shift_temp,key_m,clk: in STD_LOGIC;
q:out std_logic_vector(7 downto 0));
end component;
component kicker
Port ( clk,din : in STD_LOGIC;
d_out:out std_logic);
end component;
component shift
Port ( key_in : in STD_LOGIC;
shift_out: out std_logic_vector(3 downto 0));
end component;
component clock
Port ( clk : in STD_LOGIC;
clk_out:out std_logic_vector(3 downto 0));
end component;
signal temp:std_logic_vector(31 downto 0);
signal pinl:std_logic_vector(3 downto 0);
signal anjian:std_logic_vector(3 downto 0);
signal temp_co:std_logic_vector(2 downto 0);
signal qa,qc:std_logic;
begin
u1:count100 port map(anjian(0),pinl(1),temp(7 downto 0),temp_co(0));
u2:count60 port map(anjian(1),qa,temp_co(0),temp(15 downto 8),temp_co(1));
u3:count60 port map(anjian(2),qa,temp_co(1),temp(23 downto 16),temp_co(2));
u4:count24 port map(anjian(3),qa,temp_co(2),temp(31 downto 24));
u5:clock port map(clk,pinl);
u6:kicker port map(pinl(2),m,qa);
u7:kicker port map(pinl(2),s,qc);
u8:shift port map(qc,anjian);
data<=temp;close<=anjian(3 downto 1);
end Behavioral;
*********************8位数码管扫描**********************
entity weix is
Port ( clk : in STD_LOGIC;
close:in std_logic_vector(5 downto 0);
data : in STD_LOGIC_vector(31 downto 0);
bt : out STD_LOGIC_vector(7 downto 0);
sg: out STD_LOGIC_vector(7 downto 0));
end weix;

architecture Behavioral of weix is
signal cnt8:std_logic_vector(2 downto 0):="000";
signal temp:std_logic_vector(3 downto 0);
signal led7s:std_logic_vector(6 downto 0);
signal a:std_logic;
signal wei:std_logic_vector(7 downto 0):="11111110";
begin
process(cnt8)
begin
case cnt8 is
when"000"=>wei<="11111110";temp<=data(3 downto 0);a<='0';
when"001"=>wei<="11111101";temp<=data(7 downto 4);a<='0';
when"010"=> if close(0)='0' then wei<="11111011"; else wei<="11111111";end if;
temp<=data(11 downto 8);a<='1';
when"011"=> if close(1)='0' then wei<="11110111"; else wei<="11111111";end if;
temp<=data(15 downto 12);a<='0';
when"100"=> if close(2)='0' then wei<="11101111"; else wei<="11111111";end if;
temp<=data(19 downto 16);a<='1';
when"101"=> if close(3)='0' then wei<="11011111"; else wei<="11111111";end if;
temp<=data(23 downto 20);a<='0';
when"110"=> if close(4)='0' then wei<="10111111"; else wei<="11111111";end if;
temp<=data(27 downto 24);a<='1';
when"111"=> if close(5)='0' then wei<="01111111"; else wei<="11111111";end if;
temp<=data(31 downto 28);a<='0';
when others=>wei<= "11111111";
end case;
end process;
process(clk)
begin
if clk'event and clk='1'
then cnt8<=cnt8+1;
end if;
end process;
process(temp)
begin
case temp is
when "0000" => led7s<="0111111";
when "0001" => led7s<="0000110";
when "0010" => led7s<="1011011";
when "0011" => led7s<="1001111";
when "0100" => led7s<="1100110";
when "0101" => led7s<="1101101";
when "0110" => led7s<="1111101";
when "0111" => led7s<="0000111";
when "1000" => led7s<="1111111";
when "1001" => led7s<="1101111";
when others=>null;
end case;
end process;
sg(6 downto 0)<=led7s;sg(7)<=a;bt<=wei;
end Behavioral;
*******************电子时钟顶层文件****************
entity shizhong is
Port (oe:out std_logic_vector(2 downto 0);
er:out std_logic_vector(2 downto 0);
m,s,clk : in STD_LOGIC;
bt:out std_logic_vector(7 downto 0);
sg:out std_logic_vector(7 downto 0));
end shizhong;

architecture Behavioral of shizhong is
component count32
Port ( m,s,clk: in STD_LOGIC;
data:out std_logic_vector(31 downto 0);
close:out std_logic_vector(2 downto 0));
end component;
component clos
Port (clk:in std_logic;
q : in STD_LOGIC_vector(2 downto 0);
q_out:out std_logic_vector(5 downto 0));
end component;
component clock
Port ( clk : in STD_LOGIC;
clk_out:out std_logic_vector(3 downto 0));
end component;
component weix
Port ( clk : in STD_LOGIC;
close:in std_logic_vector(5 downto 0);
data : in STD_LOGIC_vector(31 downto 0);
bt : out STD_LOGIC_vector(7 downto 0);
sg: out STD_LOGIC_vector(7 downto 0));
end component;
signal temp:std_logic_vector(31 downto 0);
signal qa:std_logic_vector(2 downto 0);
signal qb:std_logic_vector(5 downto 0);
signal temp_clk:std_logic_vector(3 downto 0);
begin
u1:count32 port map(m,s,clk,temp,qa);
u2:weix port map(temp_clk(3),qb,temp,bt,sg);
u3:clock port map(clk,temp_clk);
u4:clos port map(temp_clk(0),qa,qb);
oe<="000";er<="110";
end Behavioral;


************索引脚******************
供参考
NET "bt" LOC = "L21" ;
NET "bt" LOC = "K22" ;
NET "bt" LOC = "K21" ;
NET "bt" LOC = "J22" ;
NET "bt" LOC = "J21" ;
NET "bt" LOC = "H22" ;
NET "bt" LOC = "H21" ;
NET "bt" LOC = "G22" ;
NET "clk" LOC = "A11" ;
NET "er" LOC = "V20" ;
NET "er" LOC = "F17" ;
NET "er" LOC = "L18" ;
NET "m" LOC = "U21" ;
NET "oe" LOC = "Y21" ;
NET "oe" LOC = "L22" ;
NET "oe" LOC = "M20" ;
NET "s" LOC = "T22" ;
NET "sg" LOC = "R21" ;
NET "sg" LOC = "R22" ;
NET "sg" LOC = "P21" ;
NET "sg" LOC = "P22" ;
NET "sg" LOC = "N21" ;
NET "sg" LOC = "N22" ;
NET "sg" LOC = "M21" ;
NET "sg" LOC = "M22" ;

基于CPLD的VHDL语言数字钟（含秒表）设计

利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试方便、故障率低、修改升级容易等特点。
本设计采用自顶向下、混合输入方式（原理图输入—顶层文件连接和VHDL语言输入—各模块程序设计）实现数字钟的设计、下载和调试。

一、 功能说明
已完成功能
1. 完成秒／分／时的依次显示并正确计数；
2. 秒／分／时各段个位满10正确进位，秒／分能做到满60向前进位；
3. 定时闹钟：实现整点报时，又扬声器发出报时声音；
4. 时间设置，也就是手动调时功能：当认为时钟不准确时，可以分别对分／时钟进行调整；
5. 利用多余两位数码管完成秒表显示：A、精度达10ms；B、可以清零；C、完成暂停
可以随时记时、暂停后记录数据。

待改进功能：
1. 闹钟只是整点报时，不能手动设置报时时间，遗憾之一；
2. 秒表不能向秒进位，也就是最多只能记时100ms；
3. 秒表暂停记录数据后不能在原有基础上继续计时，而是复位重新开始。
【注意】秒表为后来添加功能，所以有很多功能不成熟！

二、 设计方案
1. 数字钟顶层设计
外部输入要求：输入信号有1kHz／1Hz时钟信号、低电平有效的秒／微秒清零信号CLR、低电平有效的调分信号SETmin、低电平有效的调时信号SEThour；

外部输出要求：整点报时信号SOUND（59分51／3／5／7秒时未500Hz低频声，59分59秒时为1kHz高频声）、时十位显示信号h1（a,b,c,d,e,f,g）、时个位显示信号h0（a ,b,c,d,e,f,g）、分十位显示信号m1及分个位m0、秒十位s1及秒个位s0、微秒十位ms1及微秒个位ms0；数码管显示位选信号SEL0／1／2等三个信号。
2. 内部功能模块主要有：
Fenp分频模块：主要是整点报时用的1kH与500Hz的脉冲信号，这里的输入信号是1KHz信号，所以只要一个二分频即可；时间基准采用1Hz输入信号直接提供（当然也可以分频取得，这里先用的是分频取得的信号，后考虑到精度问题而采用硬件频率信号。
实现带有100进制进位和清零功能，暂定等功能的微秒模块MINSECONDB输入为1Hz脉冲和低电平的清零信号CLR与暂定信号STOP，输出微秒个位、十位及进位信号CO（虽然没有实现进位功能，但还是编写了这个端口，只是在连线时悬空）。
实现60进制带有进位和清零功能的秒计数模块SECOND，输入为1Hz脉冲和低电平有效的清零信号CLR，输出秒个位、时位及进位信号CO。
实现60进制带有进位和置数功能的分计数模块MINUTE，输入为1Hz脉冲和高电平有效的使能信号EN，输出分个位、时位及进位信号CO。
实现24进制的时计数模块HOUR，输入为1Hz脉冲和高电平有效的使能信号EN，输出分个位、时位。
实现分时复用功能模块SELTIME，输入为秒（含个／十位）、分、时、扫描时钟CLK1K，输出为D和显示控制信号SEL。
实现整点报时功能模块ALERT，输入为分／秒信号，输出为高频声控Q1K和Q500。
实现译码显示功能模块DISPLAY，输入为D，输出为Q

三、 设计框图

四、 模块说明（含程序代码）
1. 分频模块
采用原理图输入方式实现2分频与1000分频，但这里并没有用到1000分频，因为后来考虑到精度问题，将千分频用直接输入了。程序如图：利用三个7490进行硬
件分频！

2. 微秒模块
采用VHDL语言输入方式，以时钟clk，清零信号clr以及暂停信号STOP为进程敏感变量，程序如下：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MINSECONDb is
port(clk,clrm,stop:in std_logic;----时钟/清零信号
secm1,secm0:out std_logic_vector(3 downto 0);----秒高位/低位
co:out std_logic);-------输出/进位信号
end MINSECONDb;

architecture SEC of MINSECONDb is
signal clk1,DOUT2:std_logic;

begin
process(clk,clrm)
variable cnt1,cnt0:std_logic_vector(3 downto 0);---计数
VARIABLE COUNT2 :INTEGER RANGE 0 TO 10 ;
begin

IF CLK'EVENT AND CLK='1'THEN
IF COUNT2>=0 AND COUNT2<10 THEN
COUNT2:=COUNT2+1;
ELSE COUNT2:=0;
DOUT2<= NOT DOUT2;
END IF;
END IF;

if clrm='1' then----当clr为1时，高低位均为0
cnt1:="0000";
cnt0:="0000";
elsif clk'event and clk='1' then
if stop='1' then
cnt0:=cnt0;
cnt1:=cnt1;
end if;

if cnt1="1001" and cnt0="1000" then----当记数为98（实际是经过59个记时脉冲）
co<='1';----进位
cnt0:="1001";----低位为9
elsif cnt0<"1001" then----小于9时
cnt0:=cnt0+1;----计数
--elsif cnt0="1001" then
--clk1<=not clk1;
else
cnt0:="0000";

if cnt1<"1001" then----高位小于9时
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
secm1<=cnt1;
secm0<=cnt0;

end process;
end SEC;

3. 秒模块程序清单

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SECOND is
port(clk,clr:in std_logic;----时钟/清零信号
sec1,sec0:out std_logic_vector(3 downto 0);----秒高位/低位
co:out std_logic);-------输出/进位信号
end SECOND;

architecture SEC of SECOND is
begin
process(clk,clr)
variable cnt1,cnt0:std_logic_vector(3 downto 0);---计数
begin
if clr='1' then----当ckr为1时，高低位均为0
cnt1:="0000";
cnt0:="0000";
elsif clk'event and clk='1' then
if cnt1="0101" and cnt0="1000" then----当记数为58（实际是经过59个记时脉冲）
co<='1';----进位
cnt0:="1001";----低位为9
elsif cnt0<"1001" then----小于9时
cnt0:=cnt0+1;----计数
else
cnt0:="0000";

if cnt1<"0101" then----高位小于5时
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
sec1<=cnt1;
sec0<=cnt0;

end process;
end SEC;

4. 分模块程序清单

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MINUTE is
port(clk,en:in std_logic;
min1,min0:out std_logic_vector(3 downto 0);
co:out std_logic);
end MINUTE;

architecture MIN of MINUTE is
begin

process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clk'event and clk='1' then
if en='1' then
if cnt1="0101" and cnt0="1000" then
co<='1';
cnt0:="1001";
elsif cnt0<"1001" then
cnt0:=cnt0+1;
else
cnt0:="0000";

if cnt1<"0101" then
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
end if;
min1<=cnt1;
min0<=cnt0;

end process;
end MIN;

5. 时模块程序清单

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity HOUR is
port(clk,en:in std_logic;----输入时钟/高电平有效的使能信号
h1,h0:out std_logic_vector(3 downto 0));----时高位/低位
end HOUR;

architecture hour_arc of HOUR is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);----记数
begin
if clk'event and clk='1' then---上升沿触发
if en='1' then---同时“使能”为1
if cnt1="0010" and cnt0="0011" then
cnt1:="0000";----高位/低位同时为0时
cnt0:="0000";
elsif cnt0<"1001" then----低位小于9时，低位记数累加
cnt0:=cnt0+1;
else
cnt0:="0000";
cnt1:=cnt1+1;-----高位记数累加
end if;
end if;
end if;
h1<=cnt1;
h0<=cnt0;

end process;
end hour_arc;
6. 动态扫描模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity SELTIME is
port(
clk:in std_logic;------扫描时钟
secm1,secm0,sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0);-----分别为秒个位/时位；分个位/
daout:out std_logic_vector(3 downto 0);----------------输出
sel:out std_logic_vector(2 downto 0));-----位选信号
end SELTIME;
architecture fun of SELTIME is
signal count:std_logic_vector(2 downto 0);----计数信号
begin
sel<=count;
process(clk)
begin
if(clk'event and clk='1') then
if(count>="111") then
count<="000";
else
count<=count+1;
end if;
end if;
case count is
when"111"=>daout<= secm0;----秒个位
when"110"=>daout<= secm1;----秒十位
when"101"=>daout<= sec0;----分个位
when"100"=>daout<= sec1;----分十位
when"011"=>daout<=min0; ----时个位
when"010"=>daout<=min1;----时十位
when"001"=>daout<=h0;
when others =>daout<=h1;
end case;
end process;
end fun;
7. 报时模块

library ieee;
use ieee.std_logic_1164.all;
entity ALERT is
port(m1,m0,s1,s0:in std_logic_vector(3 downto 0);------输入秒、分高/低位信号
clk:in std_logic;------高频声控制
q500,qlk:out std_logic);----低频声控制
end ALERT;

architecture sss_arc of ALERT is
begin
process(clk)
begin

if clk'event and clk='1' then
if m1="0101" and m0="1001" and s1="0101" then----当秒高位为5，低位为9时且分高位为5
if s0="0001" or s0="0011" or s0="0101" or s0="0111" then---当分的低位为1或3或5或7时
q500<='1';----低频输出为1
else
q500<='0';----否则输出为0
end if;
end if;

if m1="0101" and m0="1001" and s1="0101" and s0="1001" then---当秒高位为5，低位为9时且分高位为5，----分低位为9时，也就是“59分59秒”的时候“报时”
qlk<='1';-----高频输出为1
else
qlk<='0';
end if;
end if;
end process;
end sss_arc;
8. 显示模块

library ieee;
use ieee.std_logic_1164.all;
entity DISPLAY is
port(d:in std_logic_vector(3 downto 0);----连接seltime扫描部分d信号
q:out std_logic_vector(6 downto 0));----输出段选信号（电平）
end DISPLAY;
architecture disp_are of DISPLAY is
begin
process(d)
begin

case d is
when"0000" =>q<="0111111";--显示0
when"0001" =>q<="0000110";--显示1
when"0010" =>q<="1011011";--显示2
when"0011" =>q<="1001111";--显示3
when"0100" =>q<="1100110";--显示4
when"0101" =>q<="1101101";--显示5
when"0110" =>q<="1111101";--显示6
when"0111" =>q<="0100111";--显示7
when"1000" =>q<="1111111";--显示8
when others =>q<="1101111";--显示9
end case;
end process;
end disp_are;
9. 顶层文件（原理图输入）

10.波形仿真（时序图）
五、 结论与建议
1.主要是从网上下载，借鉴后自己再根据已学的知识做检查和补充，发挥部分尚不完善。
2.微秒进位还需要改进秒模块结构以及一部分逻辑电路组成。
3.模块化设计有思路清晰、检查方便、扩展功能容易等诸多优势，且部分已经在本设计过程中得以体现。
4.如果能与单片机相结合，相信会有更好的效果，但有些时候CPLD功能比单片机强大得多。
5.总体来讲,要独立开发系统为时尚早，还需要不断学习相关EDA设计知识与技能。

六、 参考文献
1.徐向民 数字系统设计及VHDL实践 北京 机械出版社 2007.10
2.谢自美. 电子线路设计 实验 测试(第二版) 武汉 华中科技大学出版社 2002

文件名说明：
Clock.gdf为不含秒表模块的顶层文件；
Clock02.gdf为含秒表模块的顶层文件；
因已经硬件上实现功能，故这里没有仿真文件；
各模块文件名相同，但目录不同。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNTC IS
PORT(CLK,CLK0,R,BCD1WR,BCD10WR:IN STD_LOGIC;
A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Y:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END COUNTC;
ARCHITECTURE ONE OF COUNTC IS
SIGNAL BCD1N:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL BCD10N:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
P1:PROCESS(CLK,BCD1WR)
BEGIN
IF R='1' THEN
BCD1N<="0000";
ELSIF BCD1WR='1' THEN
BCD1N<=A;
ELSIF CLK'EVENT AND CLK='1' THEN
IF BCD1N="1001" THEN
BCD1N<="0000";
ELSE BCD1N<=BCD1N+1;
END IF;
END IF;
END PROCESS P1;
P2:PROCESS(CLK,BCD10WR)
BEGIN
IF R='1' THEN
BCD10N<="000";
ELSIF BCD10WR='1' THEN
BCD10N<=A(2 DOWNTO 0);
ELSIF CLK'EVENT AND CLK = '1' THEN
IF(BCD1N = "1001") THEN
IF BCD10N="101" THEN
BCD10N<="000";
ELSE BCD10N<=BCD10N+1;
END IF;
END IF;
END IF;
END PROCESS P2;
P3:PROCESS(CLK0,BCD1N,BCD10N)
BEGIN
IF CLK0 = '1' THEN
SEL <= "001";
CASE BCD1N IS
WHEN "0000"=>Y<="0111111";
WHEN "0001"=>Y<="0000110";
WHEN "0010"=>Y<="1011011";
WHEN "0011"=>Y<="1001111";
WHEN "0100"=>Y<="1100110";
WHEN "0101"=>Y<="1101101";
WHEN "0110"=>Y<="1111101";
WHEN "0111"=>Y<="0000111";
WHEN "1000"=>Y<="1111111";
WHEN "1001"=>Y<="1101111";
WHEN "1010"=>Y<="1110111";
WHEN "1011"=>Y<="1111100";
WHEN "1100"=>Y<="0111001";
WHEN "1101"=>Y<="1011110";
WHEN "1110"=>Y<="1111001";
WHEN "1111"=>Y<="1110001";
WHEN OTHERS => NULL;
END CASE;
ELSE SEL <="010";
CASE BCD10N IS
WHEN "000"=>Y<="0111111";
WHEN "001"=>Y<="0000110";
WHEN "010"=>Y<="1011011";
WHEN "011"=>Y<="1001111";
WHEN "100"=>Y<="1100110";
WHEN "101"=>Y<="1101101";
WHEN "110"=>Y<="1111101";
WHEN "111"=>Y<="0000111";
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS P3;
END ONE;

---

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