跪求vhdl编的16字符液晶显示程序
前面的4个adc条件，要输出6个t1t2t3t4的结果吗？你是不是少写了点什么？0101和1010怎么控制？
自动售货机VHDL程序
（1）自动售货机VHDL程序如下：
--文件名：pl_auto1.vhd。
--功能：货物信息存储，进程控制，硬币处理，余额计算，显示等功能。
--说明：显示的钱数coin的以5角为单位。
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PL_auto1 is
port ( clk:in std_logic; --系统时钟
set,get,sel,finish: in std_logic; --设定、买、选择、完成信号
coin0,coin1: in std_logic; --5角硬币、1元硬币
price,quantity :in std_logic_vector(3 downto 0); --价格、数量数据
item0 , act:out std_logic_vector(3 downto 0); --显示、开关信号
y0,y1 :out std_logic_vector(6 downto 0); --钱数、商品数量显示数据
act10,act5 :out std_logic); --1元硬币、5角硬币
end PL_auto1;
architecture behav of PL_auto1 is
type ram_type is array(3 downto 0)of std_logic_vector(7 downto 0);
signal ram :ram_type; --定义RAM
signal item: std_logic_vector(1 downto 0); --商品种类
signal coin: std_logic_vector(3 downto 0); --币数计数器
signal pri,qua:std_logic_vector(3 downto 0); --商品单价、数量
signal clk1: std_logic; --控制系统的时钟信号
begin
com:process(set,clk1)
variable quan:std_logic_vector(3 downto 0);
begin
if set='1' then ram(conv_integer(item))<=price & quantity;act<="0000";
--把商品的单价、数量置入到RAM
elsif clk1'event and clk1='1' then act5<='0'; act10<='0';
if coin0='1' then
if coin<"1001"then coin<=coin+1; --投入5角硬币，coin自加1
else coin<="0000";
end if;
elsif coin1='1' then
if coin<"1001"then coin<=coin+2; --投入1元硬币，coin自加2
else coin<="0000";
end if;
elsif sel='1' then item<=item+1; --对商品进行循环选择
elsif get='1' then --对商品进行购买
if qua>"0000" and coin>=pri then coin<=coin-pri;quan:=quan-1;
ram(conv_integer(item))<=pri & quan;
if item="00" then act<="1000"; --购买时，自动售货机对4种商品的操作
elsif item="01" then act<="0100";
elsif item="10" then act<="0010";
elsif item="11" then act<="0001";
end if;
end if;
elsif finish='1' then --结束交易，退币（找币）
if coin>"0001" then act10<='1';coin<=coin-2; --此IF语句完成找币操作
elsif coin>"0000" then act5<='1'; coin<=coin-1;
else act5<='0'; act10<='0';
end if;
elsif get='0' then act<="0000";
for i in 4 to 7 loop
pri(i-4)<=ram (conv_integer(item))(i); --商品单价的读取
end loop;
for i in 0 to 3 loop
quan(i):=ram(conv_integer(item))(i); --商品数量的读取
end loop;
end if;
end if;
qua<=quan;
end process com;
m32:process(clk) --此进程完成对32Mhz的脉冲分频
variable q: std_logic_vector( 24 downto 0);
begin
if clk'event and clk='1' then q:=q+1;
end if;
if q="111111111111111111111111" then clk1<='1';
else clk1<='0';
end if;
end process m32;
code0:process(item) --商品指示灯译码
begin
case item is
when "00"=>item0<="0111";
when "01"=>item0<="1011";
when "10"=>item0<="1101";
when others=>item0<="1110";
end case;
end process;
code1: process (coin) --钱数的BCD到七段码的译码
begin
case coin is
when "0000"=>y0<="0000001";
when "0001"=>y0<="1001111";
when "0010"=>y0<="0010010";
when "0011"=>y0<="0000110";
when "0100"=>y0<="1001100";
when "0101"=>y0<="0100100";
when "0110"=>y0<="0100000";
when "0111"=>y0<="0001111";
when "1000"=>y0<="0000000";
when "1001"=>y0<="0000100";
when others=>y0<="1111111";
end case;
end process;
code2: process (qua) --单价的BCD到七段码的译码
begin
case qua is
when "0000"=>y1<="0000001";
when "0001"=>y1<="1001111";
when "0010"=>y1<="0010010";
when "0011"=>y1<="0000110";
when "0100"=>y1<="1001100";
when "0101"=>y1<="0100100";
when "0110"=>y1<="0100000";
when "0111"=>y1<="0001111";
when "1000"=>y1<="0000000";
when "1001"=>y1<="0000100";
when others=>y1<="1111111";
end case;
end process;
end behav;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY basifre_product IS
PORT ( clk_1kh : IN std_logic;
fre_100h,fre_10h,fre_1h : OUT std_logic);
END basifre_product;
ARCHITECTURE stru OF basifre_product IS
COMPONENT cont10
PORT( clk,rst,en : IN std_logic;
count : OUT integer RANGE 0 TO 9 ;
ca_rry : OUT std_logic);
END COMPONENT ;
SIGNAL vcc,gnd : std_logic;
SIGNAL fre_100h_t,fre_10h_t : std_logic;
BEGIN
vcc <= '1' ;
gnd <= '0' ;
u1 : cont10 PORT MAP ( clk => clk_1kh ,rst => gnd ,en => vcc ,ca_rry => fre_100h_t ) ;
u2 : cont10 PORT MAP ( clk => fre_100h_t ,rst => gnd ,en => vcc ,ca_rry => fre_10h_t ) ;
u3 : cont10 PORT MAP ( clk => fre_10h_t ,rst => gnd ,en => vcc ,ca_rry => fre_1h ) ;
fre_100h <= fre_100h_t ;
fre_10h <= fre_10h_t ;
END stru;
--follow is mux6_1,and output is a single impluse,namely, different basic frequency
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY mux_basifre IS
PORT ( fre_1kh,fre_100h,fre_10h,fre_1h : IN std_logic ;
rst_mux_basifre,en : IN std_logic ;
sel_fre : IN integer RANGE 0 TO 3;
basi_fre : OUT std_logic );
END mux_basifre;
ARCHITECTURE beha_basifre OF mux_basifre IS
COMPONENT single_clk
PORT (cp,cd,en : IN std_logic;
q : OUT std_logic);
END COMPONENT ;
SIGNAL basi_fre_tmp,vcc : std_logic ;
BEGIN
vcc <= '1' ;
PROCESS(fre_1kh,fre_100h,fre_10h,fre_1h,en,sel_fre)
BEGIN
IF en = '0' THEN
basi_fre_tmp <= '0' ;
ELSE
CASE sel_fre IS
WHEN 0 => basi_fre_tmp <= fre_1h ;
WHEN 1 => basi_fre_tmp <= fre_10h ;
WHEN 2 => basi_fre_tmp <= fre_100h ;
WHEN 3 => basi_fre_tmp <= fre_1kh ;
WHEN OTHERS => basi_fre_tmp <= '0' ;
END CASE ;
END IF ;
END PROCESS ;
single_impluse : single_clk
PORT MAP (cp => basi_fre_tmp, cd => rst_mux_basifre,en => vcc, q => basi_fre);
END beha_basifre ;
--follow is single impluse productor,
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY t IS
PORT (cp,cd : IN std_logic;
q : OUT std_logic);
END t;
ARCHITECTURE beha OF t IS
SIGNAL qq : std_logic;
BEGIN
PROCESS (cp,cd)
BEGIN
IF cd = '1' THEN
qq<= '0' ;
ELSIF rising_edge(cp) THEN
qq<= NOT qq ;
END IF ;
END PROCESS ;
q<=qq;
END beha;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY d IS
PORT (cp,cd : IN std_logic;
q : OUT std_logic);
END d;
ARCHITECTURE beha OF d IS
SIGNAL qq : std_logic;
BEGIN
PROCESS (cp,cd)
BEGIN
IF cd = '1' THEN
qq<= '0' ;
ELSIF rising_edge(cp) THEN
qq<= '1';
END IF ;
END PROCESS;
q<=qq;
END beha;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY single_clk IS
PORT (cp,cd,en: IN std_logic;
q : OUT std_logic);
END single_clk;
ARCHITECTURE stru OF single_clk IS
COMPONENT t
PORT (cp,cd : IN std_logic;
q : OUT std_logic);
END COMPONENT ;
COMPONENT d
PORT (cp,cd : IN std_logic;
q : OUT std_logic);
END COMPONENT ;
SIGNAL q1,q2,q11,cpt : std_logic;
BEGIN
q11 <= NOT q1;
cpt <= cp AND en ;
u1: t PORT MAP (cp,cd,q1);
u2: d PORT MAP ( q11,cd,q2);
q <= q1 AND (NOT q2) ;
END stru;
--FOLLOW IS EXTER FREQUENCY CPUMTER
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY exter_fre IS
PORT ( clk_exter,rst_ex_fre,en : IN std_logic ;
cont1,cont2,cont3,cont4 : OUT integer RANGE 0 TO 9 ;
ex_ov_l,ex_ov_h : OUT std_logic);
END exter_fre;
ARCHITECTURE stru OF exter_fre IS
COMPONENT cont10
PORT( clk,rst,en : IN std_logic;
count : OUT integer RANGE 0 TO 9 ;
ca_rry : OUT std_logic);
END COMPONENT ;
SIGNAL carry1,carry2,carry3 : std_logic;
SIGNAL cont4_t,cont3_t : integer RANGE 0 TO 9 ;
SIGNAL ex_ov_h_t : std_logic;
BEGIN
u1 : cont10 PORT MAP (clk_exter , rst_ex_fre , en , cont1 , carry1 ) ;
u2 : cont10 PORT MAP ( carry1 , rst_ex_fre , en , cont2 , carry2 ) ;
u3 : cont10 PORT MAP ( carry2 , rst_ex_fre , en , cont3_t, carry3 ) ;
u4 : cont10 PORT MAP ( carry3 , rst_ex_fre , en , cont4_t, ex_ov_h_t ) ;
cont3 <= cont3_t ;
cont4 <= cont4_t ;
ex_ov_l <= '1' WHEN (cont3_t = 0) AND (cont4_t = 0) ELSE
'0' ;
PROCESS (ex_ov_h_t,rst_ex_fre)
BEGIN
IF rst_ex_fre = '1' THEN
ex_ov_h <= '0' ;
ELSIF rising_edge(ex_ov_h_t) THEN
ex_ov_h <= '1' ;
END IF ;
END PROCESS ;
END stru;
--follow is 10 counter
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY cont10 IS
PORT( clk,rst,en : IN std_logic;
count : OUT integer RANGE 0 TO 9 ;
ca_rry : OUT std_logic);
END cont10;
ARCHITECTURE beha OF cont10 IS
SIGNAL count_tem : integer RANGE 0 TO 9 ;
BEGIN
PROCESS(clk,rst,en)
BEGIN
IF rst = '1' THEN
count_tem <= 0 ;
ca_rry <= '0' ;
ELSIF rising_edge(clk) THEN
IF en = '1' THEN
IF count_tem = 9 THEN
count_tem <= 0 ;
ca_rry <= '1' ;
ELSE
count_tem <= count_tem + 1 ;
ca_rry <= '0' ;
END IF;
END IF;
END IF;
count <= count_tem ;
END PROCESS;
END beha;
--follow is cotroler,it produce istructions to control other function block
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY controler IS
PORT ( fre_10h,clk_8kh : IN std_logic ;
measure_end : IN std_logic ;
ex_ov_l,ex_ov_h : IN std_logic ;
measure,display,rst : OUT std_logic ;
alarm : OUT std_logic ;
sel_basifre : OUT integer RANGE 0 TO 3 );
END controler;
ARCHITECTURE beha_control OF controler IS
COMPONENT single_clk
PORT (cp,cd,en: IN std_logic;
q : OUT std_logic);
END COMPONENT ;
SIGNAL vcc,ov_l,ov_h,pc,display_t,display_end : std_logic;
SIGNAL display_hold_cont : integer RANGE 0 TO 9 ;
SIGNAL sel_scale_t : integer RANGE 0 TO 3 ;
BEGIN
vcc <= '1' ;
PROCESS (measure_end,ex_ov_l,ex_ov_h)
BEGIN
IF falling_edge(measure_end) THEN
ov_l <= ex_ov_l;
ov_h <= ex_ov_h ;
END IF ;
END PROCESS ;
PROCESS (measure_end,clk_8kh)
BEGIN
IF measure_end = '1' THEN
pc <= '0' ;
ELSIF rising_edge(clk_8kh) THEN
pc <= not pc ;
END IF ;
END PROCESS ;
rst_out : single_clk PORT MAP (pc, measure_end, vcc, rst);
PROCESS (pc,ov_h,ov_l,display_end)
BEGIN
IF rising_edge(pc) THEN
IF ov_h = '1' THEN
display_t <= '0' ;
measure <= '1' ;
IF sel_scale_t /= 3 THEN
sel_scale_t <= sel_scale_t + 1;
alarm <= '0' ;
ELSE
alarm <= '1' ;
END IF ;
ELSIF ov_l = '1' THEN
display_t <= '0' ;
measure <= '1' ;
IF sel_scale_t /= 0 THEN
sel_scale_t <= sel_scale_t - 1;
END IF ;
ELSE
display_t <= '1' ;
IF display_end = '1' THEN
measure <= '1' ;
ELSE
measure <= '0' ;
END IF ;
END IF ;
END IF ;
sel_basifre <= sel_scale_t ;
END PROCESS ;
display <= display_t ;
PROCESS (display_t,measure_end,fre_10h)
BEGIN
IF measure_end = '1' THEN
display_hold_cont <= 0 ;
ELSIF rising_edge(fre_10h) THEN
IF display_t = '1' THEN
IF display_hold_cont = 9 THEN
display_hold_cont <= 0 ;
display_end <= '1' ;
ELSE
display_hold_cont <= display_hold_cont + 1 ;
display_end <= '0' ;
END IF ;
END IF ;
END IF ;
END PROCESS ;
END ;
--follow is display block,
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY display IS
PORT( clk_8kh, clk_1kh,display,measure_end : IN std_logic;
ex_cont1,ex_cont2,ex_cont3,ex_cont4 : IN integer RANGE 0 TO 9 ;
sel_scale : IN integer RANGE 0 TO 3 ;
sel_led_line10, sel_led_line32 : OUT std_logic_vector(1 downto 0);
led_display_cont, led_display_scale : OUT std_logic_vector(4 downto 0));
END display ;
ARCHITECTURE beha_led OF display IS
COMPONENT scan IS
PORT ( CLKL : IN STD_LOGIC;
POINT,EXTINGGUISH : IN STD_LOGIC;
DATA : IN INTEGER RANGE 0 TO 15 ;
DISPLAY_R : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ;
SCAN_L : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) );
END COMPONENT ;
SIGNAL led_cont4_t,led_cont3_t,led_cont2_t,led_cont1_t : integer RANGE 0 TO 9 ;
SIGNAL led_data_scale,led_data_cont: integer RANGE 0 TO 15 ;
SIGNAL led_scale_t : integer RANGE 0 TO 3 ;
SIGNAL sel_led_line32_t,sel_led_line10_t1,sel_led_line10_t2: std_logic_vector(1 downto 0);
SIGNAL extingguish_scale,extingguish_cont,gnd : std_logic ;
BEGIN
gnd <= '0' ;
u_cont : scan PORT MAP
(clk_8kh, gnd, extingguish_cont, led_data_cont, led_display_cont, sel_led_line10_t1);
u_scale : scan PORT MAP
(clk_8kh, gnd, extingguish_scale, led_data_scale, led_display_scale, sel_led_line10_t2);
sel_led_line10 <= sel_led_line10_t2 ;
PROCESS(measure_end)
BEGIN
IF falling_edge(measure_end) THEN
led_scale_t <= sel_scale;
led_cont1_t <= ex_cont1 ;
led_cont2_t <= ex_cont2 ;
led_cont3_t <= ex_cont3 ;
led_cont4_t <= ex_cont4 ;
END IF;
END process ;
PROCESS(display,sel_led_line32_t,led_cont4_t,led_cont3_t,led_cont2_t,led_cont1_t)
BEGIN
IF display = '0' THEN
extingguish_cont <= '1' ;
ELSE
CASE sel_led_line32_t IS
WHEN "00" => led_data_cont <= led_cont4_t ;
IF led_cont4_t = 0 THEN
extingguish_cont <= '1' ;
ELSE
extingguish_cont <= '0' ;
END IF ;
WHEN "01" => led_data_cont <= led_cont3_t ;
IF (led_cont4_t = 0 AND led_cont3_t = 0) THEN
extingguish_cont <= '1' ;
ELSE
extingguish_cont <= '0' ;
END IF ;
WHEN "10" => led_data_cont <= led_cont2_t ;
IF (led_cont4_t = 0 AND led_cont3_t = 0 AND led_cont2_t = 0) THEN
extingguish_cont <= '1' ;
ELSE
extingguish_cont <= '0' ;
END IF ;
WHEN "11" => led_data_cont <= led_cont1_t ;
extingguish_cont <= '0' ;
WHEN OTHERS => extingguish_cont <= '1' ;
END CASE ;
END IF ;
END PROCESS ;
PROCESS(display,sel_led_line32_t,led_scale_t)
BEGIN
IF display = '0' THEN
extingguish_scale <= '1' ;
ELSE
CASE sel_led_line32_t IS
WHEN "00" =>
CASE led_scale_t IS
WHEN 0 | 3 => led_data_scale <= 1 ;
extingguish_scale <= '0' ;
WHEN 1 => led_data_scale <= 9 ;
extingguish_scale <= '0' ;
WHEN 2 => extingguish_scale <= '1' ;
WHEN OTHERS => extingguish_scale <= '1' ;
END CASE;
WHEN "01" =>
CASE led_scale_t IS
WHEN 0 | 3 => led_data_scale <= 0 ;
extingguish_scale <= '0' ;
WHEN 1 => led_data_scale <= 9 ;
extingguish_scale <= '0' ;
WHEN 2 => led_data_scale <= 1 ;
extingguish_scale <= '0' ;
WHEN OTHERS => extingguish_scale <= '1' ;
END CASE;
WHEN "10" =>
CASE led_scale_t IS
WHEN 0 | 1 => led_data_scale <= 13 ;
extingguish_scale <= '0' ;
WHEN 2 | 3 => led_data_scale <= 14 ;
extingguish_scale <= '0' ;
WHEN OTHERS => extingguish_scale <= '1' ;
END CASE;
WHEN "11" => led_data_scale <= 12 ;
extingguish_scale <= '0' ;
WHEN OTHERS => extingguish_scale <= '1' ;
END CASE ;
END IF ;
END PROCESS ;
PROCESS (clk_1kh)
BEGIN
IF rising_edge(clk_1kh) THEN
IF sel_led_line32_t = "11" THEN
sel_led_line32_t <= "00" ;
ELSE
sel_led_line32_t <= sel_led_line32_t + '1' ;
END IF ;
END IF ;
sel_led_line32 <= sel_led_line32_t ;
END PROCESS ;
END beha_led ;
--follow is 16*16 led display control
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SCAN IS
PORT ( CLKL : IN STD_LOGIC;
POINT,EXTINGGUISH : IN STD_LOGIC;
DATA : IN INTEGER RANGE 0 TO 15 ;
DISPLAY_R : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ;
SCAN_L : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) );
END SCAN;
ARCHITECTURE BEHA OF SCAN IS
SIGNAL SCAN_L_CONT : STD_LOGIC_VECTOR(1 DOWNTO 0) ;
BEGIN
PROCESS (CLKL)
BEGIN
IF RISING_EDGE(CLKL) THEN
IF SCAN_L_CONT = "11" THEN
SCAN_L_CONT <= "00" ;
ELSE
SCAN_L_CONT <= SCAN_L_CONT + '1' ;
END IF ;
END IF ;
SCAN_L <= SCAN_L_CONT ;
END PROCESS ;
--FOLLOW IS DECODE
PROCESS (SCAN_L_CONT,DATA,POINT,EXTINGGUISH)
BEGIN
IF EXTINGGUISH = '1' THEN
DISPLAY_R <= "00000" ;
ELSE
CASE SCAN_L_CONT IS
WHEN "00" =>
CASE DATA IS
WHEN 0 => DISPLAY_R <= "11111" ;
WHEN 1 => DISPLAY_R <= "00000" ;
WHEN 2 => DISPLAY_R <= "10111" ;
WHEN 3 => DISPLAY_R <= "10101" ;
WHEN 4 => DISPLAY_R <= "11100" ;
WHEN 5 => DISPLAY_R <= "11101" ;
WHEN 6 => DISPLAY_R <= "11111" ;
WHEN 7 => DISPLAY_R <= "10000" ;
WHEN 8 => DISPLAY_R <= "11111" ;
WHEN 9 => DISPLAY_R <= "11101" ;
WHEN 10 => DISPLAY_R <= "01111" ;
WHEN 11 => DISPLAY_R <= "11111" ;
--follow 3 line is for diplay C,D,E,
--but for this design,it's modified
--WHEN 12 => DISPLAY_R <= "11111" ;
--WHEN 13 => DISPLAY_R <= "00111" ;
--WHEN 14 => DISPLAY_R <= "11111" ;
WHEN 12 => DISPLAY_R <= "11111" ;
WHEN 13 => DISPLAY_R <= "11111" ;
WHEN 14 => DISPLAY_R <= "11111" ;
--above 3 line is for this design
WHEN 15 => DISPLAY_R <= "11111" ;
WHEN OTHERS => DISPLAY_R <= "00000" ;
END CASE ;
WHEN "01" =>
CASE DATA IS
WHEN 0 => DISPLAY_R <= "10001" ;
WHEN 1 => DISPLAY_R <= "00000" ;
WHEN 2 => DISPLAY_R <= "10101" ;
WHEN 3 => DISPLAY_R <= "10101" ;
WHEN 4 => DISPLAY_R <= "00100" ;
WHEN 5 => DISPLAY_R <= "10101" ;
WHEN 6 => DISPLAY_R <= "10101" ;
WHEN 7 => DISPLAY_R <= "10000" ;
WHEN 8 => DISPLAY_R <= "10101" ;
WHEN 9 => DISPLAY_R <= "10101" ;
WHEN 10 => DISPLAY_R <= "10100" ;
WHEN 11 => DISPLAY_R <= "00101" ;
--follow 3 line is for diplay C,D,E,
--but for this design,it's modified
--WHEN 12 => DISPLAY_R <= "10001" ;
--WHEN 13 => DISPLAY_R <= "00101" ;
--WHEN 14 => DISPLAY_R <= "10101" ;
WHEN 12 => DISPLAY_R <= "00100" ;
WHEN 13 => DISPLAY_R <= "01010" ;
WHEN 14 => DISPLAY_R <= "01000" ;
--above 3 line is for this design
WHEN 15 => DISPLAY_R <= "10100" ;
WHEN OTHERS => DISPLAY_R <= "00000" ;
END CASE ;
WHEN "10" =>
CASE DATA IS
WHEN 0 => DISPLAY_R <= "11111" ;
WHEN 1 => DISPLAY_R <= "11111" ;
WHEN 2 => DISPLAY_R <= "11101" ;
WHEN 3 => DISPLAY_R <= "11111" ;
WHEN 4 => DISPLAY_R <= "11111" ;
WHEN 5 => DISPLAY_R <= "10111" ;
WHEN 6 => DISPLAY_R <= "10111" ;
WHEN 7 => DISPLAY_R <= "11111" ;
WHEN 8 => DISPLAY_R <= "11111" ;
WHEN 9 => DISPLAY_R <= "11111" ;
WHEN 10 => DISPLAY_R <= "01111" ;
WHEN 11 => DISPLAY_R <= "00111" ;
--follow 3 line is for diplay C,D,E,
--but for this design,it's modified
--WHEN 12 => DISPLAY_R <= "10001" ;
--WHEN 13 => DISPLAY_R <= "11111" ;
--WHEN 14 => DISPLAY_R <= "10101" ;
WHEN 12 => DISPLAY_R <= "11111" ;
WHEN 13 => DISPLAY_R <= "10001" ;
WHEN 14 => DISPLAY_R <= "11111" ;
--above 3 line is for this design
WHEN 15 => DISPLAY_R <= "10100" ;
WHEN OTHERS => DISPLAY_R <= "00000" ;
END CASE ;
WHEN "11" => IF POINT = '1' THEN
DISPLAY_R <= "00001" ;
ELSE
DISPLAY_R <= "00000" ;
END IF ;
WHEN OTHERS => DISPLAY_R <= "00000" ;
END CASE ;
END IF ;
END PROCESS ;
END ;
--FOLLOW IS TOP ENTITY
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY frequ_er IS
PORT ( clk_1kh,clk_8kh,clk_exter : IN std_logic;
sel_led_line10, sel_led_line32 : OUT std_logic_vector(1 downto 0);
alarm : OUT std_logic ;
led_display_cont, led_display_scale : OUT std_logic_vector(4 downto 0));
END frequ_er ;
ARCHITECTURE stru OF frequ_er IS
COMPONENT basifre_product
PORT ( clk_1kh : IN std_logic;
fre_100h,fre_10h,fre_1h : OUT std_logic);
END COMPONENT ;
COMPONENT mux_basifre
PORT ( fre_1kh,fre_100h,fre_10h,fre_1h : IN std_logic ;
rst_mux_basifre,en : IN std_logic ;
sel_fre : IN integer RANGE 0 TO 3;
basi_fre : OUT std_logic );
END COMPONENT ;
COMPONENT exter_fre
PORT ( clk_exter,rst_ex_fre,en : IN std_logic ;
cont1,cont2,cont3,cont4 : OUT integer RANGE 0 TO 9 ;
ex_ov_l,ex_ov_h : OUT std_logic);
END COMPONENT ;
COMPONENT controler
PORT ( fre_10h,clk_8kh : IN std_logic ;
measure_end : IN std_logic ;
ex_ov_l,ex_ov_h : IN std_logic ;
measure,display,rst : OUT std_logic ;
alarm : OUT std_logic ;
sel_basifre : OUT integer RANGE 0 TO 3 );
END COMPONENT ;
COMPONENT display
PORT( clk_8kh, clk_1kh,display,measure_end : IN std_logic;
ex_cont1,ex_cont2,ex_cont3,ex_cont4 : IN integer RANGE 0 TO 9 ;
sel_scale : IN integer RANGE 0 TO 3 ;
sel_led_line10, sel_led_line32 : OUT std_logic_vector(1 downto 0);
led_display_cont, led_display_scale : OUT std_logic_vector(4 downto 0));
END COMPONENT ;
SIGNAL fre_100h_t,fre_10h_t,fre_1h_t : std_logic;
SIGNAL rst_t,measure_t,basi_fre_t : std_logic;
SIGNAL sel_fre_t : integer RANGE 0 TO 3;
SIGNAL ex_ov_l_t,ex_ov_h_t,display_t : std_logic ;
SIGNAL cont1_t,cont2_t,cont3_t,cont4_t : integer RANGE 0 TO 9 ;
BEGIN
BASIC_FREQUENCY_PROCUDE : basifre_product
PORT MAP (clk_1kh, fre_100h_t, fre_10h_t, fre_1h_t);
SELECT_BASIC_FREQUENCY : mux_basifre
PORT MAP (clk_1kh, fre_100h_t, fre_10h_t, fre_1h_t, rst_t,measure_t, sel_fre_t,basi_fre_t);
CENTRAL_CONTROLER : controler
PORT MAP (fre_10h_t, clk_8kh, basi_fre_t, ex_ov_l_t, ex_ov_h_t, measure_t, display_t, rst_t,
alarm,sel_fre_t);
LED_DISPLAY : display
PORT MAP (clk_8kh, clk_1kh, display_t, basi_fre_t, cont1_t, cont2_t, cont3_t, cont4_t,
sel_fre_t, sel_led_line10, sel_led_line32, led_display_cont, led_display_scale);
EXTER_FREQUENCY_COUNTER : exter_fre
PORT MAP (clk_exter, rst_t,basi_fre_t, cont1_t, cont2_t, cont3_t, cont4_t, ex_ov_l_t, ex_ov_h_t);
END stru;
关键得看你的16字液晶芯片手册。不同的硬件VHDL驱动也自然不同。但其显示原理都是一样的。
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